[PATCH] D150832: [AArch64] Predicate for ROR immediate

[Evandro Menezes via Phabricator via llvm-commits]

evandro created this revision.
evandro added reviewers: kpdev42, dmgreen, andreadb, ktkachov.
Herald added subscribers: hiraditya, kristof.beyls.
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evandro requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Add a common predicate for when the `ROR` immediate or "Bitfield extract, one register" idiom is used for `EXTR` or "Bitfield extract, two registers".


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D150832

Files:
  llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
  llvm/lib/Target/AArch64/AArch64SchedPredExynos.td
  llvm/lib/Target/AArch64/AArch64SchedPredicates.td


Index: llvm/lib/Target/AArch64/AArch64SchedPredicates.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64SchedPredicates.td
+++ llvm/lib/Target/AArch64/AArch64SchedPredicates.td
@@ -310,3 +310,8 @@
                                               CheckZeroOperand<2>]>>>],
                                       MCReturnStatement<FalsePred>>>;
 def IsZeroIdiomPred   : MCSchedPredicate<IsZeroIdiomFn>;
+
+// Identify EXTR as the alias for ROR (immediate).
+def IsRORImmIdiomPred : MCSchedPredicate<
+                          CheckAll<[CheckOpcode<[EXTRWrri, EXTRXrri]>,
+                                    CheckSameRegOperand<1, 2>]>>;
Index: llvm/lib/Target/AArch64/AArch64SchedPredExynos.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64SchedPredExynos.td
+++ llvm/lib/Target/AArch64/AArch64SchedPredExynos.td
@@ -137,11 +137,6 @@
                                IsZeroFPIdiomFn]>>>>;
 def ExynosResetPred : MCSchedPredicate<ExynosResetFn>;
 
-// Identify EXTR as the alias for ROR (immediate).
-def ExynosRotateRightImmPred : MCSchedPredicate<
-                                 CheckAll<[CheckOpcode<[EXTRWrri, EXTRXrri]>,
-                                           CheckSameRegOperand<1, 2>]>>;
-
 // Identify cheap arithmetic and logic immediate instructions.
 def ExynosCheapFn : TIIPredicate<
                       "isExynosCheapAsMove",
Index: llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
+++ llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
@@ -182,10 +182,10 @@
 def M5WriteAXX : SchedWriteVariant<[SchedVar<ExynosArithPred,   [M5WriteA1X]>,
                                     SchedVar<ExynosLogicExPred, [M5WriteA1X]>,
                                     SchedVar<NoSchedPred,       [M5WriteAAX]>]>;
-def M5WriteAYW : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M5WriteA1W]>,
-                                    SchedVar<NoSchedPred,              [M5WriteAFW]>]>;
-def M5WriteAYX : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M5WriteA1X]>,
-                                    SchedVar<NoSchedPred,              [M5WriteAFX]>]>;
+def M5WriteAYW : SchedWriteVariant<[SchedVar<IsRORImmIdiomPred, [M5WriteA1W]>,
+                                    SchedVar<NoSchedPred,       [M5WriteAFW]>]>;
+def M5WriteAYX : SchedWriteVariant<[SchedVar<IsRORImmIdiomPred, [M5WriteA1X]>,
+                                    SchedVar<NoSchedPred,       [M5WriteAFX]>]>;
 
 def M5WriteB1 : SchedWriteRes<[M5UnitB]> { let Latency = 1; }
 def M5WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M5WriteAC]>,
Index: llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
+++ llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
@@ -166,8 +166,8 @@
 def M4WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred,   [M4WriteA1]>,
                                    SchedVar<ExynosLogicExPred, [M4WriteA1]>,
                                    SchedVar<NoSchedPred,       [M4WriteAA]>]>;
-def M4WriteAY : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M4WriteA1]>,
-                                   SchedVar<NoSchedPred,              [M4WriteAF]>]>;
+def M4WriteAY : SchedWriteVariant<[SchedVar<IsRORImmIdiomPred, [M4WriteA1]>,
+                                   SchedVar<NoSchedPred,       [M4WriteAF]>]>;
 
 def M4WriteB1 : SchedWriteRes<[M4UnitB]> { let Latency = 1; }
 def M4WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M4WriteAC]>,
Index: llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
+++ llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
@@ -141,8 +141,8 @@
 def M3WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M3WriteA1]>,
                                    SchedVar<ExynosLogicPred, [M3WriteA1]>,
                                    SchedVar<NoSchedPred,     [M3WriteAA]>]>;
-def M3WriteAY : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M3WriteA1]>,
-                                   SchedVar<NoSchedPred,              [M3WriteAA]>]>;
+def M3WriteAY : SchedWriteVariant<[SchedVar<IsRORImmIdiomPred, [M3WriteA1]>,
+                                   SchedVar<NoSchedPred,       [M3WriteAA]>]>;
 
 def M3WriteB1 : SchedWriteRes<[M3UnitB]> { let Latency = 1; }
 def M3WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M3WriteAC]>,


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