[PATCH] D150824: [RISCV] Lower experimental_get_vector_length intrinsic to vsetvli for some cases.

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed May 17 15:42:12 PDT 2023

craig.topper created this revision.
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This patch lowers to vsetvli when the AVL is i32 or XLenVT and
the VF is a power of 2 in the range [1, 64]. VLEN=32 is not supported
as we don't have a valid type mapping for that. VF=1 is not supported
with Zve32* only.

The element width is used to set the SEW for the vsetvli if possible.
Otherwise we use SEW=8.

  rG LLVM Github Monorepo



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