[PATCH] D99750: [LV, VP] RFC: VP intrinsics support for the Loop Vectorizer (Proof-of-Concept)

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

> Is it possible to have multiple EVLs per vector region or will it always be a single one? Does the EVL argument need to be passed to each vector op for correctness? On RISCV, would it be sufficient/desired to set the vector length at the beginning of the vector loop?

I think it will always be a single one.

For correctness it only needs to be passed to load, store, div/rem, vp.merge, maybe some others. Computing on the whole vector with garbage elements should be ok for other arithmetic. For optimality we want to apply the same VL to every instruction.

For RISC-V we want it set at the beginning of the vector loop in the final assembly. For IR semantics, I don't think we want instructions to implicitly need to be after the instruction that sets the vector length. So we have the explicit VL operand to express the dependency. The VL from the intrinsic propagates to pseudoinstructions in the backend. The RISCVInsertVSETVLI pass uses this information as part of a dataflow analysis to determine where vsetvli instructions need to be placed and whether the VL has changed from previous instructions.


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