[PATCH] D150798: [RISCV] Implement storeOfVectorConstantIsCheap hook to prevent store merging at VL=2

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.h:538
+    // in instructions even after we add a vector constant load.
+    return NumElem >= 4;
+  }
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craig.topper wrote:
> I notice X86 uses > 2 and your patch description talks about VL=2 and mentions being similar to X86, but you've used 4 here. Is 3 supported by store merging?
All the 3 x N types are illegal, and thus not candidates for store merging. 

I mostly used 4 here as a bit of future proofing in case we decided to make odd types legal via the VP lowering which got some discussion recently.  I'm not sure that we wouldn't want VL=3 to be formed in that case, but I figured it was better not to and then revisit if desired.  (All of the cases I have where odd types would be profitable are VL=6.  Yes, all of them.)


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  https://reviews.llvm.org/D150798/new/

https://reviews.llvm.org/D150798