[llvm] 9ba918d - [RISCV] Expand testing for store merging of constant stores
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Wed May 17 09:36:13 PDT 2023
Author: Philip Reames
Date: 2023-05-17T09:36:01-07:00
New Revision: 9ba918dd1bba909c482398ae18ea45b4a1f4e3e7
URL: https://github.com/llvm/llvm-project/commit/9ba918dd1bba909c482398ae18ea45b4a1f4e3e7
DIFF: https://github.com/llvm/llvm-project/commit/9ba918dd1bba909c482398ae18ea45b4a1f4e3e7.diff
LOG: [RISCV] Expand testing for store merging of constant stores
Added:
llvm/test/CodeGen/RISCV/rvv/combine-store.ll
Modified:
Removed:
llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll b/llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll
deleted file mode 100644
index f9721538c454d..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll
+++ /dev/null
@@ -1,18 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+d,+v -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+d,+v -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s
-
-define void @combine_fp_zero_stores_crash(ptr %ptr) {
-; CHECK-LABEL: combine_fp_zero_stores_crash:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, a0, 4
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vse32.v v8, (a0)
-; CHECK-NEXT: ret
- %addr1 = getelementptr float, ptr %ptr, i64 1
- %addr2 = getelementptr float, ptr %ptr, i64 2
- store float 0.000000e+00, ptr %addr1, align 4
- store float 0.000000e+00, ptr %addr2, align 4
- ret void
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/combine-store.ll b/llvm/test/CodeGen/RISCV/rvv/combine-store.ll
new file mode 100644
index 0000000000000..59de2206e4345
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/combine-store.ll
@@ -0,0 +1,176 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d,+v -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck --check-prefixes=CHECK,RV32 %s
+; RUN: llc -mtriple=riscv64 -mattr=+d,+v -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck --check-prefixes=CHECK,RV64 %s
+
+define void @combine_zero_stores_2xi8(ptr %p) {
+; CHECK-LABEL: combine_zero_stores_2xi8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sh zero, 0(a0)
+; CHECK-NEXT: ret
+ store i8 zeroinitializer, ptr %p, align 4
+ %gep = getelementptr i8, ptr %p, i64 1
+ store i8 zeroinitializer, ptr %gep
+ ret void
+}
+
+define void @combine_zero_stores_2xi16(ptr %p) {
+; CHECK-LABEL: combine_zero_stores_2xi16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sw zero, 0(a0)
+; CHECK-NEXT: ret
+ store i16 zeroinitializer, ptr %p, align 4
+ %gep = getelementptr i8, ptr %p, i64 2
+ store i16 zeroinitializer, ptr %gep
+ ret void
+}
+
+define void @combine_zero_stores_2xi32(ptr %p) {
+; RV32-LABEL: combine_zero_stores_2xi32:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: vse32.v v8, (a0)
+; RV32-NEXT: ret
+;
+; RV64-LABEL: combine_zero_stores_2xi32:
+; RV64: # %bb.0:
+; RV64-NEXT: sd zero, 0(a0)
+; RV64-NEXT: ret
+ store i32 zeroinitializer, ptr %p, align 8
+ %gep = getelementptr i8, ptr %p, i64 4
+ store i32 zeroinitializer, ptr %gep
+ ret void
+}
+
+define void @combine_zero_stores_2xi32_unaligned(ptr %p) {
+; RV32-LABEL: combine_zero_stores_2xi32_unaligned:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: vse32.v v8, (a0)
+; RV32-NEXT: ret
+;
+; RV64-LABEL: combine_zero_stores_2xi32_unaligned:
+; RV64: # %bb.0:
+; RV64-NEXT: sw zero, 0(a0)
+; RV64-NEXT: sw zero, 4(a0)
+; RV64-NEXT: ret
+ store i32 zeroinitializer, ptr %p
+ %gep = getelementptr i8, ptr %p, i64 4
+ store i32 zeroinitializer, ptr %gep
+ ret void
+}
+
+define void @combine_zero_stores_2xi64(ptr %p) {
+; RV32-LABEL: combine_zero_stores_2xi64:
+; RV32: # %bb.0:
+; RV32-NEXT: sw zero, 4(a0)
+; RV32-NEXT: sw zero, 0(a0)
+; RV32-NEXT: sw zero, 12(a0)
+; RV32-NEXT: sw zero, 8(a0)
+; RV32-NEXT: ret
+;
+; RV64-LABEL: combine_zero_stores_2xi64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: vse64.v v8, (a0)
+; RV64-NEXT: ret
+ store i64 zeroinitializer, ptr %p
+ %gep = getelementptr i8, ptr %p, i64 8
+ store i64 zeroinitializer, ptr %gep
+ ret void
+}
+
+define void @combine_fp_zero_stores_crash(ptr %ptr) {
+; CHECK-LABEL: combine_fp_zero_stores_crash:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, a0, 4
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vse32.v v8, (a0)
+; CHECK-NEXT: ret
+ %addr1 = getelementptr float, ptr %ptr, i64 1
+ %addr2 = getelementptr float, ptr %ptr, i64 2
+ store float 0.000000e+00, ptr %addr1, align 4
+ store float 0.000000e+00, ptr %addr2, align 4
+ ret void
+}
+
+define void @combine_allones_stores_2xi8(ptr %p) {
+; CHECK-LABEL: combine_allones_stores_2xi8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a1, -1
+; CHECK-NEXT: sh a1, 0(a0)
+; CHECK-NEXT: ret
+ store i8 -1, ptr %p, align 4
+ %gep = getelementptr i8, ptr %p, i64 1
+ store i8 -1, ptr %gep
+ ret void
+}
+
+define void @combine_allones_stores_2xi16(ptr %p) {
+; CHECK-LABEL: combine_allones_stores_2xi16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a1, -1
+; CHECK-NEXT: sw a1, 0(a0)
+; CHECK-NEXT: ret
+ store i16 -1, ptr %p, align 4
+ %gep = getelementptr i8, ptr %p, i64 2
+ store i16 -1, ptr %gep
+ ret void
+}
+
+define void @combine_allones_stores_2xi32(ptr %p) {
+; RV32-LABEL: combine_allones_stores_2xi32:
+; RV32: # %bb.0:
+; RV32-NEXT: li a1, -1
+; RV32-NEXT: sw a1, 0(a0)
+; RV32-NEXT: sw a1, 4(a0)
+; RV32-NEXT: ret
+;
+; RV64-LABEL: combine_allones_stores_2xi32:
+; RV64: # %bb.0:
+; RV64-NEXT: li a1, -1
+; RV64-NEXT: sd a1, 0(a0)
+; RV64-NEXT: ret
+ store i32 -1, ptr %p, align 8
+ %gep = getelementptr i8, ptr %p, i64 4
+ store i32 -1, ptr %gep
+ ret void
+}
+
+define void @combine_allones_stores_2xi32_unaligned(ptr %p) {
+; CHECK-LABEL: combine_allones_stores_2xi32_unaligned:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a1, -1
+; CHECK-NEXT: sw a1, 0(a0)
+; CHECK-NEXT: sw a1, 4(a0)
+; CHECK-NEXT: ret
+ store i32 -1, ptr %p
+ %gep = getelementptr i8, ptr %p, i64 4
+ store i32 -1, ptr %gep
+ ret void
+}
+
+define void @combine_allones_stores_2xi64(ptr %p) {
+; RV32-LABEL: combine_allones_stores_2xi64:
+; RV32: # %bb.0:
+; RV32-NEXT: li a1, -1
+; RV32-NEXT: sw a1, 4(a0)
+; RV32-NEXT: sw a1, 0(a0)
+; RV32-NEXT: sw a1, 12(a0)
+; RV32-NEXT: sw a1, 8(a0)
+; RV32-NEXT: ret
+;
+; RV64-LABEL: combine_allones_stores_2xi64:
+; RV64: # %bb.0:
+; RV64-NEXT: li a1, -1
+; RV64-NEXT: sd a1, 0(a0)
+; RV64-NEXT: sd a1, 8(a0)
+; RV64-NEXT: ret
+ store i64 -1, ptr %p
+ %gep = getelementptr i8, ptr %p, i64 8
+ store i64 -1, ptr %gep
+ ret void
+}
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