[PATCH] D150788: [AMDGPU][GlobalISel] Rematerialze constants with different regbank

[Mirko Brkusanin via Phabricator via llvm-commits]

mbrkusanin created this revision.
mbrkusanin added reviewers: foad, arsenm.
mbrkusanin added a project: LLVM.
Herald added subscribers: StephenFan, kerbowa, hiraditya, tpr, dstuttard, yaxunl, jvesely, kzhuravl.
Herald added a project: All.
mbrkusanin requested review of this revision.
Herald added a subscriber: wdng.

Constants which are mapped by default to SGPRs will require a copy to an
VPGR if they have a VGPR use. By rematerializing the instructions with the
appropriate bank we can avoid cross regbank copies.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D150788

Files:
  llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
  llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
  llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot2.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant32bit.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
  llvm/test/CodeGen/AMDGPU/constrained-shift.ll
  llvm/test/CodeGen/AMDGPU/ctlz.ll
  llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll
  llvm/test/CodeGen/AMDGPU/cttz.ll
  llvm/test/CodeGen/AMDGPU/ds-alignment.ll
  llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
  llvm/test/CodeGen/AMDGPU/fma.f16.ll
  llvm/test/CodeGen/AMDGPU/lds-atomic-fmin-fmax.ll
  llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
  llvm/test/CodeGen/AMDGPU/mad-mix.ll
  llvm/test/CodeGen/AMDGPU/remat-fp64-constants.ll
  llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll