[PATCH] D150769: [SelectionDAG][computeKnownBits]: Move ISD::ADD/ISD::SUB into their own cases

[Dhruv Chawla via Phabricator via llvm-commits]

0xdc03 added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:3637-3643
+    KnownBits KnownOp0 =
+        computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
+    KnownBits KnownOp1 =
+        computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
+    Known = KnownBits::computeForAddSub(Op.getOpcode() == ISD::ADD,
+                                        Flags.hasNoSignedWrap(), KnownOp0,
+                                        KnownOp1);
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nikic wrote:
> There are pre-defined variables to put the operand known bits in, if there's just two.
Fixed, thanks!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150769/new/

https://reviews.llvm.org/D150769