[PATCH] D150771: [RISCV] Set Fast flag for unaligned scalar memory accesses

[Luke Lau via Phabricator via llvm-commits]

luke created this revision.
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The +unaligned-scalar-mem feature was added in
https://reviews.llvm.org/D126085 to allow subtargets to indicate that
they supported misaligned loads/stores with "sufficient" performance.
This is separate from whether or not the target actually supports
misaligned accesses, which could be determined from Zicclsm.

This patch then enables the Fast flag under the assumption that any subtarget
that declares support for +unaligned-scalar-mem will want to opt into
optimisations that take advantrage of misaligned scalar accesses, such as store
merging.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D150771

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/memcpy-inline.ll
  llvm/test/CodeGen/RISCV/unaligned-load-store.ll

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