[PATCH] D150768: [SVE ACLE] Canonicalise SVE merging intrinsics
Jolanta Jensen via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed May 17 03:53:55 PDT 2023
jolanta.jensen created this revision.
jolanta.jensen added reviewers: mgabka, paulwalker-arm.
Herald added subscribers: ctetreau, hiraditya, tschuett.
Herald added a project: All.
jolanta.jensen requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.
Canonicalise SVE merging intrinsics to their equivalent
undef (_u) variants when they take an all active predicate.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D150768
Files:
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
Index: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -1265,11 +1265,21 @@
static std::optional<Instruction *> instCombineSVEVectorAdd(InstCombiner &IC,
IntrinsicInst &II) {
+ if (auto FMLA_U =
+ instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_fmul_u,
+ Intrinsic::aarch64_sve_fmla_u>(
+ IC, II, true))
+ return FMLA_U;
if (auto FMLA =
instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_fmul,
Intrinsic::aarch64_sve_fmla>(IC, II,
true))
return FMLA;
+ if (auto MLA_U =
+ instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_mul_u,
+ Intrinsic::aarch64_sve_mla_u>(
+ IC, II, true))
+ return MLA_U;
if (auto MLA = instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_mul,
Intrinsic::aarch64_sve_mla>(
IC, II, true))
@@ -1288,11 +1298,21 @@
static std::optional<Instruction *> instCombineSVEVectorSub(InstCombiner &IC,
IntrinsicInst &II) {
+ if (auto FMLS_U =
+ instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_fmul_u,
+ Intrinsic::aarch64_sve_fmls_u>(
+ IC, II, true))
+ return FMLS_U;
if (auto FMLS =
instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_fmul,
Intrinsic::aarch64_sve_fmls>(IC, II,
true))
return FMLS;
+ if (auto MLS_U =
+ instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_mul_u,
+ Intrinsic::aarch64_sve_mls_u>(
+ IC, II, true))
+ return MLS_U;
if (auto MLS = instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_mul,
Intrinsic::aarch64_sve_mls>(
IC, II, true))
@@ -1677,27 +1697,15 @@
case Intrinsic::aarch64_sve_fmul:
return instCombineSVEVectorMul(IC, II);
case Intrinsic::aarch64_sve_fadd:
- case Intrinsic::aarch64_sve_add:
- return instCombineSVEVectorAdd(IC, II);
case Intrinsic::aarch64_sve_fadd_u:
- return instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_fmul_u,
- Intrinsic::aarch64_sve_fmla_u>(
- IC, II, true);
+ case Intrinsic::aarch64_sve_add:
case Intrinsic::aarch64_sve_add_u:
- return instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_mul_u,
- Intrinsic::aarch64_sve_mla_u>(
- IC, II, true);
+ return instCombineSVEVectorAdd(IC, II);
case Intrinsic::aarch64_sve_fsub:
- case Intrinsic::aarch64_sve_sub:
- return instCombineSVEVectorSub(IC, II);
case Intrinsic::aarch64_sve_fsub_u:
- return instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_fmul_u,
- Intrinsic::aarch64_sve_fmls_u>(
- IC, II, true);
+ case Intrinsic::aarch64_sve_sub:
case Intrinsic::aarch64_sve_sub_u:
- return instCombineSVEVectorFuseMulAddSub<Intrinsic::aarch64_sve_mul_u,
- Intrinsic::aarch64_sve_mls_u>(
- IC, II, true);
+ return instCombineSVEVectorSub(IC, II);
case Intrinsic::aarch64_sve_tbl:
return instCombineSVETBL(IC, II);
case Intrinsic::aarch64_sve_uunpkhi:
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