[PATCH] D150717: [RISCV] Use scalar stores for splats of zero to memory up to XLen

[Philip Reames via Phabricator via llvm-commits]

reames updated this revision to Diff 522873.
reames retitled this revision from "[RISCV] Use scalar stores for splats of zero to memory upto 2 x XLen" to "[RISCV] Use scalar stores for splats of zero to memory up to XLen".
reames edited the summary of this revision.
reames added a comment.

Noticed while looking at something else that DAG combine store merging will produce the <2 x i64> vector stores this is splitting.  The particular test case came from memset lowering.  Oddly, this seeming conflict appears to work out, but it feels like we should really fix the store merging preference before handling the two stores part of this.

(following is removed from review description as it no longer applies, saved only for my later reference)

One concern here is that splitting the store into two instructions could introduce a store-to-load forwarding stall.  I think this is worth doing, but what do others think?  Should we restrict this to a maximum of XLEN sized operations which can be done in a single store?

This transform is potentially increasing the number of memory operations (from 1 to 2).  The same restriction mentioned above would resolve this as well.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150717/new/

https://reviews.llvm.org/D150717

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll

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