[llvm] 64c938e - [AMDGPU] Avoid RegScavenger::forward in copyPhysReg/indirectCopyToAGPR

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2023-05-16T15:51:31+01:00
New Revision: 64c938e8e31d311829c525b77e05dfd798c8d88f

URL: https://github.com/llvm/llvm-project/commit/64c938e8e31d311829c525b77e05dfd798c8d88f
DIFF: https://github.com/llvm/llvm-project/commit/64c938e8e31d311829c525b77e05dfd798c8d88f.diff

LOG: [AMDGPU] Avoid RegScavenger::forward in copyPhysReg/indirectCopyToAGPR

RegScavenger::backward is preferred because it does not rely on accurate
kill flags.

Differential Revision: https://reviews.llvm.org/D150571

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 4f695a88027a6..a38a835fd196e 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -618,8 +618,8 @@ static void indirectCopyToAGPR(const SIInstrInfo &TII,
     }
   }
 
-  RS.enterBasicBlock(MBB);
-  RS.forward(MI);
+  RS.enterBasicBlockEnd(MBB);
+  RS.backward(MI);
 
   // Ideally we want to have three registers for a long reg_sequence copy
   // to hide 2 waitstates between v_mov_b32 and accvgpr_write.