[llvm] b5f2bc2 - [GlobalIsel][x86] Legalize G_AND, G_OR, and G_XOR for AVX2
Thorsten Schütt via llvm-commits
llvm-commits at lists.llvm.org
Tue May 16 05:40:09 PDT 2023
Author: Thorsten Schütt
Date: 2023-05-16T14:40:01+02:00
New Revision: b5f2bc2ddfaafa8b5230af4a7dda6d6f441b8722
URL: https://github.com/llvm/llvm-project/commit/b5f2bc2ddfaafa8b5230af4a7dda6d6f441b8722
DIFF: https://github.com/llvm/llvm-project/commit/b5f2bc2ddfaafa8b5230af4a7dda6d6f441b8722.diff
LOG: [GlobalIsel][x86] Legalize G_AND, G_OR, and G_XOR for AVX2
check plan: ninja check-llvm-codegen-x86
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D150658
Added:
llvm/test/CodeGen/X86/GlobalISel/legalize-and-or-xor.mir
Modified:
llvm/lib/Target/X86/X86LegalizerInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86LegalizerInfo.cpp b/llvm/lib/Target/X86/X86LegalizerInfo.cpp
index 2fd740573d244..dbe939709ff3b 100644
--- a/llvm/lib/Target/X86/X86LegalizerInfo.cpp
+++ b/llvm/lib/Target/X86/X86LegalizerInfo.cpp
@@ -465,6 +465,9 @@ void X86LegalizerInfo::setLegalizerInfoAVX2() {
LegacyLegalizeActions::Legal);
LegacyInfo.setAction({G_UNMERGE_VALUES, Ty}, LegacyLegalizeActions::Legal);
}
+
+ getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
+ .legalFor({v8s32, v4s64});
}
void X86LegalizerInfo::setLegalizerInfoAVX512() {
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-and-or-xor.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-and-or-xor.mir
new file mode 100644
index 0000000000000..5e9ede0c485c7
--- /dev/null
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-and-or-xor.mir
@@ -0,0 +1,149 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
+# RUN: llc -O0 -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s
+
+# test vpand
+
+---
+name: test_and_v8s32
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+body: |
+ bb.1:
+
+ ; CHECK-LABEL: name: test_and_v8s32
+ ; CHECK: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<8 x s32>) = G_AND [[DEF]], [[DEF]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY [[AND]](<8 x s32>)
+ ; CHECK-NEXT: RET 0, implicit [[COPY]](<8 x s32>)
+ %0:_(<8 x s32>) = IMPLICIT_DEF
+ %1:_(<8 x s32>) = G_AND %0, %0
+ %2:_(<8 x s32>) = COPY %1(<8 x s32>)
+ RET 0, implicit %2
+...
+---
+name: test_and_v4s64
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+body: |
+ bb.1:
+
+ ; CHECK-LABEL: name: test_and_v4s64
+ ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s64>) = G_AND [[DEF]], [[DEF]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY [[AND]](<4 x s64>)
+ ; CHECK-NEXT: RET 0, implicit [[COPY]](<4 x s64>)
+ %0:_(<4 x s64>) = IMPLICIT_DEF
+ %1:_(<4 x s64>) = G_AND %0, %0
+ %2:_(<4 x s64>) = COPY %1(<4 x s64>)
+ RET 0, implicit %2
+...
+---
+name: test_xor_v4s64
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: test_xor_v4s64
+ ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s64>) = G_XOR [[DEF]], [[DEF]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY [[XOR]](<4 x s64>)
+ ; CHECK-NEXT: RET 0, implicit [[COPY]](<4 x s64>)
+ %0:_(<4 x s64>) = IMPLICIT_DEF
+ %1:_(<4 x s64>) = G_XOR %0, %0
+ %2:_(<4 x s64>) = COPY %1(<4 x s64>)
+ RET 0, implicit %2
+
+...
+---
+name: test_xor_v8s32
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: test_xor_v8s32
+ ; CHECK: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<8 x s32>) = G_XOR [[DEF]], [[DEF]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY [[XOR]](<8 x s32>)
+ ; CHECK-NEXT: RET 0, implicit [[COPY]](<8 x s32>)
+ %0:_(<8 x s32>) = IMPLICIT_DEF
+ %1:_(<8 x s32>) = G_XOR %0, %0
+ %2:_(<8 x s32>) = COPY %1(<8 x s32>)
+ RET 0, implicit %2
+
+...
+---
+name: test_or_v4s64
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: test_or_v4s64
+ ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s64>) = G_OR [[DEF]], [[DEF]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY [[OR]](<4 x s64>)
+ ; CHECK-NEXT: RET 0, implicit [[COPY]](<4 x s64>)
+ %0:_(<4x s64>) = IMPLICIT_DEF
+ %1:_(<4x s64>) = G_OR %0, %0
+ %2:_(<4x s64>) = COPY %1(<4x s64>)
+ RET 0, implicit %2
+
+...
+---
+name: test_or_v8s32
+alignment: 16
+legalized: false
+regBankSelected: false
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+liveins:
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: test_or_v8s32
+ ; CHECK: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<8 x s32>) = G_OR [[DEF]], [[DEF]]
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY [[OR]](<8 x s32>)
+ ; CHECK-NEXT: RET 0, implicit [[COPY]](<8 x s32>)
+ %0:_(<8x s32>) = IMPLICIT_DEF
+ %1:_(<8x s32>) = G_OR %0, %0
+ %2:_(<8x s32>) = COPY %1(<8x s32>)
+ RET 0, implicit %2
+
+...
More information about the llvm-commits
mailing list