[llvm] dadb77b - [AArch64] Regenerate test checks (NFC)

[Nikita Popov via llvm-commits]

Author: Nikita Popov
Date: 2023-05-16T10:29:36+02:00
New Revision: dadb77b626cd04d749487b3e2711fb23e5d17200

URL: https://github.com/llvm/llvm-project/commit/dadb77b626cd04d749487b3e2711fb23e5d17200
DIFF: https://github.com/llvm/llvm-project/commit/dadb77b626cd04d749487b3e2711fb23e5d17200.diff

LOG: [AArch64] Regenerate test checks (NFC)

Added: 
    

Modified: 
    llvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-sextinreg.mir

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-sextinreg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-sextinreg.mir
index e79939ffcb9fc..aea2dd91184c7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-sextinreg.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-sextinreg.mir
@@ -13,12 +13,13 @@ body:             |
     liveins: $w0
     ; CHECK-LABEL: name: sextinreg_ashr_to_sbfx
     ; CHECK: liveins: $w0
-    ; CHECK: %x:_(s32) = COPY $w0
-    ; CHECK: %lsb:_(s32) = G_CONSTANT i32 5
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
-    ; CHECK: %sext_inreg:_(s32) = G_SBFX %x, %lsb(s32), [[C]]
-    ; CHECK: $w0 = COPY %sext_inreg(s32)
-    ; CHECK: RET_ReallyLR implicit $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %x:_(s32) = COPY $w0
+    ; CHECK-NEXT: %lsb:_(s32) = G_CONSTANT i32 5
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
+    ; CHECK-NEXT: %sext_inreg:_(s32) = G_SBFX %x, %lsb(s32), [[C]]
+    ; CHECK-NEXT: $w0 = COPY %sext_inreg(s32)
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %x:_(s32) = COPY $w0
     %lsb:_(s32) = G_CONSTANT i32 5
     %shift:_(s32) = G_ASHR %x, %lsb
@@ -36,12 +37,13 @@ body:             |
     liveins: $w0
     ; CHECK-LABEL: name: sextinreg_lshr_to_sbfx
     ; CHECK: liveins: $w0
-    ; CHECK: %x:_(s32) = COPY $w0
-    ; CHECK: %lsb:_(s32) = G_CONSTANT i32 5
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
-    ; CHECK: %sext_inreg:_(s32) = G_SBFX %x, %lsb(s32), [[C]]
-    ; CHECK: $w0 = COPY %sext_inreg(s32)
-    ; CHECK: RET_ReallyLR implicit $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %x:_(s32) = COPY $w0
+    ; CHECK-NEXT: %lsb:_(s32) = G_CONSTANT i32 5
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
+    ; CHECK-NEXT: %sext_inreg:_(s32) = G_SBFX %x, %lsb(s32), [[C]]
+    ; CHECK-NEXT: $w0 = COPY %sext_inreg(s32)
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %x:_(s32) = COPY $w0
     %lsb:_(s32) = G_CONSTANT i32 5
     %shift:_(s32) = G_LSHR %x, %lsb
@@ -62,12 +64,13 @@ body:             |
 
     ; CHECK-LABEL: name: dont_apply_no_constant
     ; CHECK: liveins: $w0
-    ; CHECK: %x:_(s32) = COPY $w0
-    ; CHECK: %y:_(s32) = COPY $w0
-    ; CHECK: %shift:_(s32) = G_LSHR %x, %y(s32)
-    ; CHECK: %sext_inreg:_(s32) = G_SEXT_INREG %shift, 10
-    ; CHECK: $w0 = COPY %sext_inreg(s32)
-    ; CHECK: RET_ReallyLR implicit $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %x:_(s32) = COPY $w0
+    ; CHECK-NEXT: %y:_(s32) = COPY $w0
+    ; CHECK-NEXT: %shift:_(s32) = G_LSHR %x, %y(s32)
+    ; CHECK-NEXT: %sext_inreg:_(s32) = G_SEXT_INREG %shift, 10
+    ; CHECK-NEXT: $w0 = COPY %sext_inreg(s32)
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %x:_(s32) = COPY $w0
     %y:_(s32) = COPY $w0
     %shift:_(s32) = G_LSHR %x, %y
@@ -88,12 +91,13 @@ body:             |
 
     ; CHECK-LABEL: name: dont_apply_shift_imm_too_large
     ; CHECK: liveins: $w0
-    ; CHECK: %x:_(s32) = COPY $w0
-    ; CHECK: %lsb:_(s32) = G_CONSTANT i32 32
-    ; CHECK: %shift:_(s32) = G_ASHR %x, %lsb(s32)
-    ; CHECK: %sext_inreg:_(s32) = G_SEXT_INREG %shift, 1
-    ; CHECK: $w0 = COPY %sext_inreg(s32)
-    ; CHECK: RET_ReallyLR implicit $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %x:_(s32) = COPY $w0
+    ; CHECK-NEXT: %lsb:_(s32) = G_CONSTANT i32 32
+    ; CHECK-NEXT: %shift:_(s32) = G_ASHR %x, %lsb(s32)
+    ; CHECK-NEXT: %sext_inreg:_(s32) = G_SEXT_INREG %shift, 1
+    ; CHECK-NEXT: $w0 = COPY %sext_inreg(s32)
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %x:_(s32) = COPY $w0
     %lsb:_(s32) = G_CONSTANT i32 32
     %shift:_(s32) = G_ASHR %x, %lsb
@@ -114,12 +118,13 @@ body:             |
 
     ; CHECK-LABEL: name: dont_apply_negative_shift_imm
     ; CHECK: liveins: $w0
-    ; CHECK: %x:_(s32) = COPY $w0
-    ; CHECK: %lsb:_(s32) = G_CONSTANT i32 -1
-    ; CHECK: %shift:_(s32) = G_ASHR %x, %lsb(s32)
-    ; CHECK: %sext_inreg:_(s32) = G_SEXT_INREG %shift, 1
-    ; CHECK: $w0 = COPY %sext_inreg(s32)
-    ; CHECK: RET_ReallyLR implicit $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %x:_(s32) = COPY $w0
+    ; CHECK-NEXT: %lsb:_(s32) = G_CONSTANT i32 -1
+    ; CHECK-NEXT: %shift:_(s32) = G_ASHR %x, %lsb(s32)
+    ; CHECK-NEXT: %sext_inreg:_(s32) = G_SEXT_INREG %shift, 1
+    ; CHECK-NEXT: $w0 = COPY %sext_inreg(s32)
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %x:_(s32) = COPY $w0
     %lsb:_(s32) = G_CONSTANT i32 -1
     %shift:_(s32) = G_ASHR %x, %lsb
@@ -137,13 +142,14 @@ body:             |
     liveins: $w0
     ; CHECK-LABEL: name: dont_apply_more_than_one_use
     ; CHECK: liveins: $w0
-    ; CHECK: %x:_(s32) = COPY $w0
-    ; CHECK: %lsb:_(s32) = G_CONSTANT i32 1
-    ; CHECK: %shift:_(s32) = G_ASHR %x, %lsb(s32)
-    ; CHECK: %sext_inreg:_(s32) = G_SEXT_INREG %shift, 1
-    ; CHECK: %mul:_(s32) = G_MUL %shift, %sext_inreg
-    ; CHECK: $w0 = COPY %mul(s32)
-    ; CHECK: RET_ReallyLR implicit $w0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %x:_(s32) = COPY $w0
+    ; CHECK-NEXT: %lsb:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: %shift:_(s32) = G_ASHR %x, %lsb(s32)
+    ; CHECK-NEXT: %sext_inreg:_(s32) = G_SEXT_INREG %shift, 1
+    ; CHECK-NEXT: %mul:_(s32) = G_MUL %shift, %sext_inreg
+    ; CHECK-NEXT: $w0 = COPY %mul(s32)
+    ; CHECK-NEXT: RET_ReallyLR implicit $w0
     %x:_(s32) = COPY $w0
     %lsb:_(s32) = G_CONSTANT i32 1
     %shift:_(s32) = G_ASHR %x, %lsb