[PATCH] D150562: [RISCV] Avoid RegScavenger::forward in RISCVMakeCompressibleOpt
Jay Foad via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue May 16 01:13:14 PDT 2023
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG8cf5f730fb02: [RISCV] Avoid RegScavenger::forward in RISCVMakeCompressibleOpt (authored by foad).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D150562/new/
https://reviews.llvm.org/D150562
Files:
llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
Index: llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+++ llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
@@ -227,9 +227,6 @@
const TargetRegisterInfo *TRI =
MBB.getParent()->getSubtarget().getRegisterInfo();
- RegScavenger RS;
- RS.enterBasicBlock(MBB);
-
for (MachineBasicBlock::instr_iterator I = FirstMI.getIterator(),
E = MBB.instr_end();
I != E; ++I) {
@@ -238,14 +235,8 @@
// Determine if this is an instruction which would benefit from using the
// new register.
RegImmPair CandidateRegImm = getRegImmPairPreventingCompression(MI);
- if (CandidateRegImm.Reg == RegImm.Reg &&
- CandidateRegImm.Imm == RegImm.Imm) {
- // Advance tracking since the value in the new register must be live for
- // this instruction too.
- RS.forward(I);
-
+ if (CandidateRegImm.Reg == RegImm.Reg && CandidateRegImm.Imm == RegImm.Imm)
MIs.push_back(&MI);
- }
// If RegImm.Reg is modified by this instruction, then we cannot optimize
// past this instruction. If the register is already compressed, then it may
@@ -278,6 +269,9 @@
else
return RISCV::NoRegister;
+ RegScavenger RS;
+ RS.enterBasicBlockEnd(MBB);
+ RS.backward(MIs.back()->getIterator());
return RS.scavengeRegisterBackwards(*RCToScavenge, FirstMI.getIterator(),
/*RestoreAfter=*/false, /*SPAdj=*/0,
/*AllowSpill=*/false);
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