[PATCH] D147107: [InstCombine] Add test cases for `(rem (shl Y, X), (shl Z, X))`; NFC

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n updated this revision to Diff 522306.
goldstein.w.n added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147107/new/

https://reviews.llvm.org/D147107

Files:
  llvm/test/Transforms/InstCombine/rem-mul-shl.ll


Index: llvm/test/Transforms/InstCombine/rem-mul-shl.ll
===================================================================
--- llvm/test/Transforms/InstCombine/rem-mul-shl.ll
+++ llvm/test/Transforms/InstCombine/rem-mul-shl.ll
@@ -49,6 +49,19 @@
   ret i8 %r
 }
 
+define i8 @urem_XY_XZ_with_CY_rem_CZ_eq_0_with_shl(i8 %X) {
+; CHECK-LABEL: @urem_XY_XZ_with_CY_rem_CZ_eq_0_with_shl(
+; CHECK-NEXT:    [[BO0:%.*]] = shl nuw i8 15, [[X:%.*]]
+; CHECK-NEXT:    [[BO1:%.*]] = shl i8 5, [[X]]
+; CHECK-NEXT:    [[R:%.*]] = urem i8 [[BO0]], [[BO1]]
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %BO0 = shl nuw i8 15, %X
+  %BO1 = shl i8 5, %X
+  %r = urem i8 %BO0, %BO1
+  ret i8 %r
+}
+
 define i8 @urem_XY_XZ_with_CY_rem_CZ_eq_0_fail_missing_flag(i8 %X) {
 ; CHECK-LABEL: @urem_XY_XZ_with_CY_rem_CZ_eq_0_fail_missing_flag(
 ; CHECK-NEXT:    [[BO0:%.*]] = mul nsw i8 [[X:%.*]], 15
@@ -73,6 +86,19 @@
   ret i8 %r
 }
 
+define i8 @urem_XY_XZ_with_CY_lt_CZ_with_shl(i8 %X) {
+; CHECK-LABEL: @urem_XY_XZ_with_CY_lt_CZ_with_shl(
+; CHECK-NEXT:    [[BO0:%.*]] = shl i8 3, [[X:%.*]]
+; CHECK-NEXT:    [[BO1:%.*]] = shl nuw i8 12, [[X]]
+; CHECK-NEXT:    [[R:%.*]] = urem i8 [[BO0]], [[BO1]]
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %BO0 = shl i8 3, %X
+  %BO1 = shl nuw i8 12, %X
+  %r = urem i8 %BO0, %BO1
+  ret i8 %r
+}
+
 define <2 x i8> @urem_XY_XZ_with_CY_lt_CZ_with_nsw_out(<2 x i8> %X) {
 ; CHECK-LABEL: @urem_XY_XZ_with_CY_lt_CZ_with_nsw_out(
 ; CHECK-NEXT:    [[R:%.*]] = shl nuw nsw <2 x i8> [[X:%.*]], <i8 2, i8 2>
@@ -281,6 +307,19 @@
   ret i8 %r
 }
 
+define <2 x i8> @srem_XY_XZ_with_CY_lt_CZ_with_nuw_out_with_shl(<2 x i8> %X) {
+; CHECK-LABEL: @srem_XY_XZ_with_CY_lt_CZ_with_nuw_out_with_shl(
+; CHECK-NEXT:    [[BO0:%.*]] = shl nuw <2 x i8> <i8 3, i8 3>, [[X:%.*]]
+; CHECK-NEXT:    [[BO1:%.*]] = shl nsw <2 x i8> <i8 15, i8 15>, [[X]]
+; CHECK-NEXT:    [[R:%.*]] = srem <2 x i8> [[BO0]], [[BO1]]
+; CHECK-NEXT:    ret <2 x i8> [[R]]
+;
+  %BO0 = shl nuw <2 x i8> <i8 3, i8 3>, %X
+  %BO1 = shl nsw <2 x i8> <i8 15, i8 15>, %X
+  %r = srem <2 x i8> %BO0, %BO1
+  ret <2 x i8> %r
+}
+
 define i8 @srem_XY_XZ_with_CY_lt_CZ_no_nsw_out(i8 %X) {
 ; CHECK-LABEL: @srem_XY_XZ_with_CY_lt_CZ_no_nsw_out(
 ; CHECK-NEXT:    [[R:%.*]] = mul nsw i8 [[X:%.*]], 5


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