[PATCH] D150550: [RISCV] Refactor predicates for rvv intrinsic patterns.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVFeatures.td:456
+
+def HasVInstructionsFullMultify : Predicate<"Subtarget->hasVInstructionsFullMultify()">,
+      AssemblerPredicate<
----------------
Multify -> Multiply


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Comment at: llvm/lib/Target/RISCV/RISCVFeatures.td:457
+def HasVInstructionsFullMultify : Predicate<"Subtarget->hasVInstructionsFullMultify()">,
+      AssemblerPredicate<
+          (any_of FeatureStdExtV),
----------------
I don't think you need an assembler predicate. This is only use for CodeGenOnly pseudos.


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Comment at: llvm/lib/Target/RISCV/RISCVFeatures.td:467
+def HasVInstructionsF16 : Predicate<"Subtarget->hasVInstructionsF16()">,
+      AssemblerPredicate<
+          (any_of FeatureStdExtZvfh),
----------------
You don't need an AssemblerPredicate


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:4468
       defvar fti = vtiTofti.Fti;
+    let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
+                                 GetVTypePredicates<fti>.Predicates) in {
----------------
Can reduce the indentation of the 2 defvars above


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:4751
       defvar inst = instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW # "_" # emul_str;
+    let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
+                                 GetVTypePredicates<ivti>.Predicates) in
----------------
Fix the indentation


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:5633
+  let Predicates = GetVTypePredicates<vti>.Predicates in {
   def : Pat<(vti.Vector (int_riscv_vrsub (vti.Vector (undef)),
                                          (vti.Vector vti.RegClass:$rs2),
----------------
Indent since you create a new scope


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:6344
+  let Predicates = GetVTypePredicates<vti>.Predicates in {
   def : Pat<(vti.Vector (int_riscv_vsll (vti.Vector undef),
                                         (vti.Vector vti.RegClass:$rs1),
----------------
Indent


Repository:
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  https://reviews.llvm.org/D150550/new/

https://reviews.llvm.org/D150550