[PATCH] D150562: [RISCV] Avoid RegScavenger::forward in RISCVMakeCompressibleOpt

Jay Foad via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon May 15 05:50:37 PDT 2023

foad created this revision.
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RegScavenger::backward is preferred because it does not rely on accurate
kill flags.

  rG LLVM Github Monorepo



Index: llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
--- llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+++ llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
@@ -227,9 +227,6 @@
   const TargetRegisterInfo *TRI =
-  RegScavenger RS;
-  RS.enterBasicBlock(MBB);
   for (MachineBasicBlock::instr_iterator I = FirstMI.getIterator(),
                                          E = MBB.instr_end();
        I != E; ++I) {
@@ -238,14 +235,8 @@
     // Determine if this is an instruction which would benefit from using the
     // new register.
     RegImmPair CandidateRegImm = getRegImmPairPreventingCompression(MI);
-    if (CandidateRegImm.Reg == RegImm.Reg &&
-        CandidateRegImm.Imm == RegImm.Imm) {
-      // Advance tracking since the value in the new register must be live for
-      // this instruction too.
-      RS.forward(I);
+    if (CandidateRegImm.Reg == RegImm.Reg && CandidateRegImm.Imm == RegImm.Imm)
-    }
     // If RegImm.Reg is modified by this instruction, then we cannot optimize
     // past this instruction. If the register is already compressed, then it may
@@ -278,6 +269,9 @@
     return RISCV::NoRegister;
+  RegScavenger RS;
+  RS.enterBasicBlockEnd(MBB);
+  RS.backward(MIs.back()->getIterator());
   return RS.scavengeRegisterBackwards(*RCToScavenge, FirstMI.getIterator(),
                                       /*RestoreAfter=*/false, /*SPAdj=*/0,

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