[PATCH] D145218: Can SubRangeJoin, attribute of JoinVals, be modified by target? Why is this attribute set to false now?

[michael_zhang via Phabricator via llvm-commits]

Michael-Zhang-21 updated this revision to Diff 522100.
Michael-Zhang-21 added a comment.
Herald added a reviewer: gkistanova.

1、SubRangeJoin cannot be set to true in JoinVirtRegs function. Becuase it will check Live Ranges of a virtual register. When set to true, virtual reg with subranges will all be set to CR_Replace without LaneMask conflicting check. Thus, SubRangeJoin can not be set by Target.

2、I met a IR like this:
3504B	bb.16.for.body62:
	; predecessors: %bb.15, %bb.16

  	  successors: %bb.17(0x04000000), %bb.16(0x7c000000); %bb.17(3.12%), %bb.16(96.88%)

...
3872B	  %72.ssub_0:v64_regs = Vector_Calc_Op %72.ssub_0:v64_regs
3904B	  %239:v32_regs = Vector_Calc_Op %239:v32_regs
4256B	  BNE %263:scalar_regs, $r0, %bb.16

...
4272B	bb.17.for.cond71.preheader:
	; predecessors: %bb.16

  	  successors: %bb.19; %bb.19(100.00%)

4304B	  %72.ssub_1:v64_regs = COPY %239:v32_regs
4320B	  %237:v64_regs = IMPLICIT_DEF
4336B	  %238:v64_regs = COPY %72:v64_regs

------------------------

Here, we are doing JoinVirtRegs function for this MI: 4304B	  %72.ssub_1:v64_regs = COPY %239:v32_regs.
Although %72 and %239 has conflicting LR, But they are conflicting in different Lanes. Only ssub0 of %72 is conflicting in 3872B, but not the ssub1 of %72 which is what we care about.
The reason why it fails is that PHI-def LR's LaneMask is set to 0xFFFFFFFF. But in this case, the VNI is not Live in all SubRanges. When considering about the LaneMask of this PHI-def LR, we can caculate the LaneMask which VNI is just living in. Other Subranges should have nothing with this VNI.

After modification, the IR looks like this :
3504B	bb.16.for.body62:
	; predecessors: %bb.15, %bb.16

  	  successors: %bb.17(0x04000000), %bb.16(0x7c000000); %bb.17(3.12%), %bb.16(96.88%)

...
3872B	  %72.ssub_0:v64_regs = Vector_Calc_Op %72.ssub_0:v64_regs
3904B	  %72.ssub_1:v64_regs = Vector_Calc_Op %72.ssub_1:v64_regs
4256B	  BNE %263:scalar_regs, $r0, %bb.16

...
4272B	bb.17.for.cond71.preheader:
	; predecessors: %bb.16

  	  successors: %bb.19; %bb.19(100.00%)

4320B	  %237:v64_regs = IMPLICIT_DEF
4336B	  %238:v64_regs = COPY %72:v64_regs

Please review~
--------------

3、Met a case in AMDGPU: llvm/test/CodeGen/AMDGPU/coalescer-subranges-prune-kill-copy.mir
IR:

  bb.0:
    undef %0.sub0:vreg_128 = IMPLICIT_DEF
    %0.sub1:vreg_128 = IMPLICIT_DEF
    %1:vreg_128 = COPY %0
    %2:vreg_128 = COPY killed %0
    S_BRANCH %bb.2

 -----

Analysis:
%1 and %2 should be identical values.
But in JoinVals::followCopyChain, %0 has subranges. The program will return in if (LRQ.valueIn() && ValueIn != LRQ.valueIn()) condition.
But the function returns TrackReg which is %1 and %2 respectively.
When %0 doesnot have subranges, func will return SrcReg, %0.
I think in subranges branch, it should return the final def values, which is SrcReg and VNI should be updated with LRQ.valueIn().


Repository:
  rZORG LLVM Github Zorg

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145218/new/

https://reviews.llvm.org/D145218

Files:
  llvm/lib/CodeGen/RegisterCoalescer.cpp


Index: llvm/lib/CodeGen/RegisterCoalescer.cpp
===================================================================
--- llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -2477,8 +2477,11 @@
           ValueIn = LRQ.valueIn();
           continue;
         }
-        if (LRQ.valueIn() && ValueIn != LRQ.valueIn())
+        if (LRQ.valueIn() && ValueIn != LRQ.valueIn()) {
+          VNI = LRQ.valueIn();
+          TrackReg = SrcReg;
           return std::make_pair(VNI, TrackReg);
+        }
       }
     }
     if (ValueIn == nullptr) {
@@ -2536,6 +2539,16 @@
     // Conservatively assume that all lanes in a PHI are valid.
     LaneBitmask Lanes = SubRangeJoin ? LaneBitmask::getLane(0)
                                      : TRI->getSubRegIndexLaneMask(SubIdx);
+    if (!SubRangeJoin && LIS->getInterval(Reg).hasSubRanges()) {
+      Lanes = LaneBitmask::getNone();
+      for(auto subrangeIt = LIS->getInterval(Reg).subrange_begin();
+          subrangeIt != LIS->getInterval(Reg).subrange_end();
+          subrangeIt++){
+        if (subrangeIt->liveAt(VNI->def)) {
+          Lanes |= subrangeIt->LaneMask;
+        }
+      }
+    }
     V.ValidLanes = V.WriteLanes = Lanes;
   } else {
     DefMI = Indexes->getInstructionFromIndex(VNI->def);


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