[PATCH] D149646: [LLVM][Uniformity] Propagate temporal divergence explicitly

[Sameer Sahasrabuddhe via Phabricator via llvm-commits]

sameerds marked 3 inline comments as done.
sameerds added inline comments.


================
Comment at: llvm/lib/CodeGen/MachineUniformityAnalysis.cpp:117-136
+void llvm::GenericUniformityAnalysisImpl<MachineSSAContext>::
+    propagateTemporalDivergence(const MachineInstr &I,
+                                const MachineCycle &DefCycle) {
+  const auto &RegInfo = F.getRegInfo();
+  for (auto &Op : I.operands()) {
+    if (!Op.isReg() || !Op.isDef())
+      continue;
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yassingh wrote:
> Is the case described in the summary also triggering for MIR? If yes maybe you can add a relevant test.
I just tried adding an identical MIR test. Unfortunately, it runs into the problem with SI_LOOP that is being fixed in D150438. I'll add the test to that review.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149646/new/

https://reviews.llvm.org/D149646