[llvm] 6e6bed5 - [RISCV] Add test cases for forming vfwmacc when widening from f16 to f64. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun May 14 22:41:28 PDT 2023
Author: Craig Topper
Date: 2023-05-14T22:35:39-07:00
New Revision: 6e6bed575777be7be55482090414e153ed6f7557
URL: https://github.com/llvm/llvm-project/commit/6e6bed575777be7be55482090414e153ed6f7557
DIFF: https://github.com/llvm/llvm-project/commit/6e6bed575777be7be55482090414e153ed6f7557.diff
LOG: [RISCV] Add test cases for forming vfwmacc when widening from f16 to f64. NFC
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
index cc9a8f037956a..1c2230fd30dee 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll
@@ -1310,3 +1310,720 @@ define <8 x double> @vfwnmsac_fv_v8f64(<8 x double> %va, <8 x float> %vb, float
%vg = call <8 x double> @llvm.fma.v8f64(<8 x double> %vd, <8 x double> %vf, <8 x double> %va)
ret <8 x double> %vg
}
+
+define <1 x double> @vfwmacc_vv_v1f64_v1f16(<1 x double> %va, <1 x half> %vb, <1 x half> %vc) {
+; CHECK-LABEL: vfwmacc_vv_v1f64_v1f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; CHECK-NEXT: vfwcvt.f.f.v v11, v9
+; CHECK-NEXT: vfwcvt.f.f.v v9, v10
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwmacc.vv v8, v11, v9
+; CHECK-NEXT: ret
+ %vd = fpext <1 x half> %vb to <1 x double>
+ %ve = fpext <1 x half> %vc to <1 x double>
+ %vf = call <1 x double> @llvm.fma.v1f64(<1 x double> %vd, <1 x double> %ve, <1 x double> %va)
+ ret <1 x double> %vf
+}
+
+define <1 x double> @vfwmacc_vf_v1f64_v1f16(<1 x double> %va, <1 x half> %vb, half %c) {
+; CHECK-LABEL: vfwmacc_vf_v1f64_v1f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v11, v9
+; CHECK-NEXT: vfwcvt.f.f.v v9, v10
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwmacc.vv v8, v11, v9
+; CHECK-NEXT: ret
+ %head = insertelement <1 x half> poison, half %c, i32 0
+ %splat = shufflevector <1 x half> %head, <1 x half> poison, <1 x i32> zeroinitializer
+ %vd = fpext <1 x half> %vb to <1 x double>
+ %ve = fpext <1 x half> %splat to <1 x double>
+ %vf = call <1 x double> @llvm.fma.v1f64(<1 x double> %vd, <1 x double> %ve, <1 x double> %va)
+ ret <1 x double> %vf
+}
+
+define <1 x double> @vfwnmacc_vv_v1f64_v1f16(<1 x double> %va, <1 x half> %vb, <1 x half> %vc) {
+; CHECK-LABEL: vfwnmacc_vv_v1f64_v1f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; CHECK-NEXT: vfwcvt.f.f.v v11, v9
+; CHECK-NEXT: vfwcvt.f.f.v v9, v10
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwnmacc.vv v8, v11, v9
+; CHECK-NEXT: ret
+ %vd = fpext <1 x half> %vb to <1 x double>
+ %ve = fpext <1 x half> %vc to <1 x double>
+ %vf = fneg <1 x double> %va
+ %vg = fneg <1 x double> %vd
+ %vh = call <1 x double> @llvm.fma.v1f64(<1 x double> %vg, <1 x double> %ve, <1 x double> %vf)
+ ret <1 x double> %vh
+}
+
+define <1 x double> @vfwnmacc_vf_v1f64_v1f16(<1 x double> %va, <1 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmacc_vf_v1f64_v1f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v11, v9
+; CHECK-NEXT: vfwcvt.f.f.v v9, v10
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwnmacc.vv v8, v11, v9
+; CHECK-NEXT: ret
+ %head = insertelement <1 x half> poison, half %c, i32 0
+ %splat = shufflevector <1 x half> %head, <1 x half> poison, <1 x i32> zeroinitializer
+ %vd = fpext <1 x half> %vb to <1 x double>
+ %ve = fpext <1 x half> %splat to <1 x double>
+ %vf = fneg <1 x double> %va
+ %vg = fneg <1 x double> %vd
+ %vh = call <1 x double> @llvm.fma.v1f64(<1 x double> %vg, <1 x double> %ve, <1 x double> %vf)
+ ret <1 x double> %vh
+}
+
+define <1 x double> @vfwnmacc_fv_v1f64_v1f16(<1 x double> %va, <1 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmacc_fv_v1f64_v1f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v11, v9
+; CHECK-NEXT: vfwcvt.f.f.v v9, v10
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwnmacc.vv v8, v11, v9
+; CHECK-NEXT: ret
+ %head = insertelement <1 x half> poison, half %c, i32 0
+ %splat = shufflevector <1 x half> %head, <1 x half> poison, <1 x i32> zeroinitializer
+ %vd = fpext <1 x half> %vb to <1 x double>
+ %ve = fpext <1 x half> %splat to <1 x double>
+ %vf = fneg <1 x double> %va
+ %vg = fneg <1 x double> %ve
+ %vh = call <1 x double> @llvm.fma.v1f64(<1 x double> %vd, <1 x double> %vg, <1 x double> %vf)
+ ret <1 x double> %vh
+}
+
+define <1 x double> @vfwmsac_vv_v1f64_v1f16(<1 x double> %va, <1 x half> %vb, <1 x half> %vc) {
+; CHECK-LABEL: vfwmsac_vv_v1f64_v1f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; CHECK-NEXT: vfwcvt.f.f.v v11, v9
+; CHECK-NEXT: vfwcvt.f.f.v v9, v10
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwmsac.vv v8, v11, v9
+; CHECK-NEXT: ret
+ %vd = fpext <1 x half> %vb to <1 x double>
+ %ve = fpext <1 x half> %vc to <1 x double>
+ %vf = fneg <1 x double> %va
+ %vg = call <1 x double> @llvm.fma.v1f64(<1 x double> %vd, <1 x double> %ve, <1 x double> %vf)
+ ret <1 x double> %vg
+}
+
+define <1 x double> @vfwmsac_vf_v1f64_v1f16(<1 x double> %va, <1 x half> %vb, half %c) {
+; CHECK-LABEL: vfwmsac_vf_v1f64_v1f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v11, v9
+; CHECK-NEXT: vfwcvt.f.f.v v9, v10
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwmsac.vv v8, v11, v9
+; CHECK-NEXT: ret
+ %head = insertelement <1 x half> poison, half %c, i32 0
+ %splat = shufflevector <1 x half> %head, <1 x half> poison, <1 x i32> zeroinitializer
+ %vd = fpext <1 x half> %vb to <1 x double>
+ %ve = fpext <1 x half> %splat to <1 x double>
+ %vf = fneg <1 x double> %va
+ %vg = call <1 x double> @llvm.fma.v1f64(<1 x double> %vd, <1 x double> %ve, <1 x double> %vf)
+ ret <1 x double> %vg
+}
+
+define <1 x double> @vfwnmsac_vv_v1f64_v1f16(<1 x double> %va, <1 x half> %vb, <1 x half> %vc) {
+; CHECK-LABEL: vfwnmsac_vv_v1f64_v1f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; CHECK-NEXT: vfwcvt.f.f.v v11, v9
+; CHECK-NEXT: vfwcvt.f.f.v v9, v10
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwnmsac.vv v8, v11, v9
+; CHECK-NEXT: ret
+ %vd = fpext <1 x half> %vb to <1 x double>
+ %ve = fpext <1 x half> %vc to <1 x double>
+ %vf = fneg <1 x double> %vd
+ %vg = call <1 x double> @llvm.fma.v1f64(<1 x double> %vf, <1 x double> %ve, <1 x double> %va)
+ ret <1 x double> %vg
+}
+
+define <1 x double> @vfwnmsac_vf_v1f64_v1f16(<1 x double> %va, <1 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmsac_vf_v1f64_v1f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v11, v9
+; CHECK-NEXT: vfwcvt.f.f.v v9, v10
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwnmsac.vv v8, v11, v9
+; CHECK-NEXT: ret
+ %head = insertelement <1 x half> poison, half %c, i32 0
+ %splat = shufflevector <1 x half> %head, <1 x half> poison, <1 x i32> zeroinitializer
+ %vd = fpext <1 x half> %vb to <1 x double>
+ %ve = fpext <1 x half> %splat to <1 x double>
+ %vf = fneg <1 x double> %vd
+ %vg = call <1 x double> @llvm.fma.v1f64(<1 x double> %vf, <1 x double> %ve, <1 x double> %va)
+ ret <1 x double> %vg
+}
+
+define <1 x double> @vfwnmsac_fv_v1f64_v1f16(<1 x double> %va, <1 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmsac_fv_v1f64_v1f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v11, v9
+; CHECK-NEXT: vfwcvt.f.f.v v9, v10
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwnmsac.vv v8, v11, v9
+; CHECK-NEXT: ret
+ %head = insertelement <1 x half> poison, half %c, i32 0
+ %splat = shufflevector <1 x half> %head, <1 x half> poison, <1 x i32> zeroinitializer
+ %vd = fpext <1 x half> %vb to <1 x double>
+ %ve = fpext <1 x half> %splat to <1 x double>
+ %vf = fneg <1 x double> %ve
+ %vg = call <1 x double> @llvm.fma.v1f64(<1 x double> %vd, <1 x double> %vf, <1 x double> %va)
+ ret <1 x double> %vg
+}
+
+define <2 x double> @vfwmacc_vv_v2f64_v2f16(<2 x double> %va, <2 x half> %vb, <2 x half> %vc) {
+; CHECK-LABEL: vfwmacc_vv_v2f64_v2f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vfwcvt.f.f.v v11, v9
+; CHECK-NEXT: vfwcvt.f.f.v v9, v10
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwmacc.vv v8, v11, v9
+; CHECK-NEXT: ret
+ %vd = fpext <2 x half> %vb to <2 x double>
+ %ve = fpext <2 x half> %vc to <2 x double>
+ %vf = call <2 x double> @llvm.fma.v2f64(<2 x double> %vd, <2 x double> %ve, <2 x double> %va)
+ ret <2 x double> %vf
+}
+
+define <2 x double> @vfwmacc_vf_v2f64_v2f16(<2 x double> %va, <2 x half> %vb, half %c) {
+; CHECK-LABEL: vfwmacc_vf_v2f64_v2f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v11, v9
+; CHECK-NEXT: vfwcvt.f.f.v v9, v10
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwmacc.vv v8, v11, v9
+; CHECK-NEXT: ret
+ %head = insertelement <2 x half> poison, half %c, i32 0
+ %splat = shufflevector <2 x half> %head, <2 x half> poison, <2 x i32> zeroinitializer
+ %vd = fpext <2 x half> %vb to <2 x double>
+ %ve = fpext <2 x half> %splat to <2 x double>
+ %vf = call <2 x double> @llvm.fma.v2f64(<2 x double> %vd, <2 x double> %ve, <2 x double> %va)
+ ret <2 x double> %vf
+}
+
+define <2 x double> @vfwnmacc_vv_v2f64_v2f16(<2 x double> %va, <2 x half> %vb, <2 x half> %vc) {
+; CHECK-LABEL: vfwnmacc_vv_v2f64_v2f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vfwcvt.f.f.v v11, v9
+; CHECK-NEXT: vfwcvt.f.f.v v9, v10
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwnmacc.vv v8, v11, v9
+; CHECK-NEXT: ret
+ %vd = fpext <2 x half> %vb to <2 x double>
+ %ve = fpext <2 x half> %vc to <2 x double>
+ %vf = fneg <2 x double> %va
+ %vg = fneg <2 x double> %vd
+ %vh = call <2 x double> @llvm.fma.v2f64(<2 x double> %vg, <2 x double> %ve, <2 x double> %vf)
+ ret <2 x double> %vh
+}
+
+define <2 x double> @vfwnmacc_vf_v2f64_v2f16(<2 x double> %va, <2 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmacc_vf_v2f64_v2f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v11, v9
+; CHECK-NEXT: vfwcvt.f.f.v v9, v10
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwnmacc.vv v8, v11, v9
+; CHECK-NEXT: ret
+ %head = insertelement <2 x half> poison, half %c, i32 0
+ %splat = shufflevector <2 x half> %head, <2 x half> poison, <2 x i32> zeroinitializer
+ %vd = fpext <2 x half> %vb to <2 x double>
+ %ve = fpext <2 x half> %splat to <2 x double>
+ %vf = fneg <2 x double> %va
+ %vg = fneg <2 x double> %vd
+ %vh = call <2 x double> @llvm.fma.v2f64(<2 x double> %vg, <2 x double> %ve, <2 x double> %vf)
+ ret <2 x double> %vh
+}
+
+define <2 x double> @vfwnmacc_fv_v2f64_v2f16(<2 x double> %va, <2 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmacc_fv_v2f64_v2f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v11, v9
+; CHECK-NEXT: vfwcvt.f.f.v v9, v10
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwnmacc.vv v8, v11, v9
+; CHECK-NEXT: ret
+ %head = insertelement <2 x half> poison, half %c, i32 0
+ %splat = shufflevector <2 x half> %head, <2 x half> poison, <2 x i32> zeroinitializer
+ %vd = fpext <2 x half> %vb to <2 x double>
+ %ve = fpext <2 x half> %splat to <2 x double>
+ %vf = fneg <2 x double> %va
+ %vg = fneg <2 x double> %ve
+ %vh = call <2 x double> @llvm.fma.v2f64(<2 x double> %vd, <2 x double> %vg, <2 x double> %vf)
+ ret <2 x double> %vh
+}
+
+define <2 x double> @vfwmsac_vv_v2f64_v2f16(<2 x double> %va, <2 x half> %vb, <2 x half> %vc) {
+; CHECK-LABEL: vfwmsac_vv_v2f64_v2f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vfwcvt.f.f.v v11, v9
+; CHECK-NEXT: vfwcvt.f.f.v v9, v10
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwmsac.vv v8, v11, v9
+; CHECK-NEXT: ret
+ %vd = fpext <2 x half> %vb to <2 x double>
+ %ve = fpext <2 x half> %vc to <2 x double>
+ %vf = fneg <2 x double> %va
+ %vg = call <2 x double> @llvm.fma.v2f64(<2 x double> %vd, <2 x double> %ve, <2 x double> %vf)
+ ret <2 x double> %vg
+}
+
+define <2 x double> @vfwmsac_vf_v2f64_v2f16(<2 x double> %va, <2 x half> %vb, half %c) {
+; CHECK-LABEL: vfwmsac_vf_v2f64_v2f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v11, v9
+; CHECK-NEXT: vfwcvt.f.f.v v9, v10
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwmsac.vv v8, v11, v9
+; CHECK-NEXT: ret
+ %head = insertelement <2 x half> poison, half %c, i32 0
+ %splat = shufflevector <2 x half> %head, <2 x half> poison, <2 x i32> zeroinitializer
+ %vd = fpext <2 x half> %vb to <2 x double>
+ %ve = fpext <2 x half> %splat to <2 x double>
+ %vf = fneg <2 x double> %va
+ %vg = call <2 x double> @llvm.fma.v2f64(<2 x double> %vd, <2 x double> %ve, <2 x double> %vf)
+ ret <2 x double> %vg
+}
+
+define <2 x double> @vfwnmsac_vv_v2f64_v2f16(<2 x double> %va, <2 x half> %vb, <2 x half> %vc) {
+; CHECK-LABEL: vfwnmsac_vv_v2f64_v2f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vfwcvt.f.f.v v11, v9
+; CHECK-NEXT: vfwcvt.f.f.v v9, v10
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwnmsac.vv v8, v11, v9
+; CHECK-NEXT: ret
+ %vd = fpext <2 x half> %vb to <2 x double>
+ %ve = fpext <2 x half> %vc to <2 x double>
+ %vf = fneg <2 x double> %vd
+ %vg = call <2 x double> @llvm.fma.v2f64(<2 x double> %vf, <2 x double> %ve, <2 x double> %va)
+ ret <2 x double> %vg
+}
+
+define <2 x double> @vfwnmsac_vf_v2f64_v2f16(<2 x double> %va, <2 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmsac_vf_v2f64_v2f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v11, v9
+; CHECK-NEXT: vfwcvt.f.f.v v9, v10
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwnmsac.vv v8, v11, v9
+; CHECK-NEXT: ret
+ %head = insertelement <2 x half> poison, half %c, i32 0
+ %splat = shufflevector <2 x half> %head, <2 x half> poison, <2 x i32> zeroinitializer
+ %vd = fpext <2 x half> %vb to <2 x double>
+ %ve = fpext <2 x half> %splat to <2 x double>
+ %vf = fneg <2 x double> %vd
+ %vg = call <2 x double> @llvm.fma.v2f64(<2 x double> %vf, <2 x double> %ve, <2 x double> %va)
+ ret <2 x double> %vg
+}
+
+define <2 x double> @vfwnmsac_fv_v2f64_v2f16(<2 x double> %va, <2 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmsac_fv_v2f64_v2f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vfmv.v.f v10, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v11, v9
+; CHECK-NEXT: vfwcvt.f.f.v v9, v10
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwnmsac.vv v8, v11, v9
+; CHECK-NEXT: ret
+ %head = insertelement <2 x half> poison, half %c, i32 0
+ %splat = shufflevector <2 x half> %head, <2 x half> poison, <2 x i32> zeroinitializer
+ %vd = fpext <2 x half> %vb to <2 x double>
+ %ve = fpext <2 x half> %splat to <2 x double>
+ %vf = fneg <2 x double> %ve
+ %vg = call <2 x double> @llvm.fma.v2f64(<2 x double> %vd, <2 x double> %vf, <2 x double> %va)
+ ret <2 x double> %vg
+}
+
+
+define <4 x double> @vfwmacc_vv_v4f64_v4f16(<4 x double> %va, <4 x half> %vb, <4 x half> %vc) {
+; CHECK-LABEL: vfwmacc_vv_v4f64_v4f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vfwcvt.f.f.v v12, v10
+; CHECK-NEXT: vfwcvt.f.f.v v10, v11
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfwmacc.vv v8, v12, v10
+; CHECK-NEXT: ret
+ %vd = fpext <4 x half> %vb to <4 x double>
+ %ve = fpext <4 x half> %vc to <4 x double>
+ %vf = call <4 x double> @llvm.fma.v4f64(<4 x double> %vd, <4 x double> %ve, <4 x double> %va)
+ ret <4 x double> %vf
+}
+
+define <4 x double> @vfwmacc_vf_v4f64_v4f16(<4 x double> %va, <4 x half> %vb, half %c) {
+; CHECK-LABEL: vfwmacc_vf_v4f64_v4f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vfmv.v.f v11, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v12, v10
+; CHECK-NEXT: vfwcvt.f.f.v v10, v11
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfwmacc.vv v8, v12, v10
+; CHECK-NEXT: ret
+ %head = insertelement <4 x half> poison, half %c, i32 0
+ %splat = shufflevector <4 x half> %head, <4 x half> poison, <4 x i32> zeroinitializer
+ %vd = fpext <4 x half> %vb to <4 x double>
+ %ve = fpext <4 x half> %splat to <4 x double>
+ %vf = call <4 x double> @llvm.fma.v4f64(<4 x double> %vd, <4 x double> %ve, <4 x double> %va)
+ ret <4 x double> %vf
+}
+
+define <4 x double> @vfwnmacc_vv_v4f64_v4f16(<4 x double> %va, <4 x half> %vb, <4 x half> %vc) {
+; CHECK-LABEL: vfwnmacc_vv_v4f64_v4f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vfwcvt.f.f.v v12, v10
+; CHECK-NEXT: vfwcvt.f.f.v v10, v11
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfwnmacc.vv v8, v12, v10
+; CHECK-NEXT: ret
+ %vd = fpext <4 x half> %vb to <4 x double>
+ %ve = fpext <4 x half> %vc to <4 x double>
+ %vf = fneg <4 x double> %va
+ %vg = fneg <4 x double> %vd
+ %vh = call <4 x double> @llvm.fma.v4f64(<4 x double> %vg, <4 x double> %ve, <4 x double> %vf)
+ ret <4 x double> %vh
+}
+
+define <4 x double> @vfwnmacc_vf_v4f64_v4f16(<4 x double> %va, <4 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmacc_vf_v4f64_v4f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vfmv.v.f v11, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v12, v10
+; CHECK-NEXT: vfwcvt.f.f.v v10, v11
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfwnmacc.vv v8, v12, v10
+; CHECK-NEXT: ret
+ %head = insertelement <4 x half> poison, half %c, i32 0
+ %splat = shufflevector <4 x half> %head, <4 x half> poison, <4 x i32> zeroinitializer
+ %vd = fpext <4 x half> %vb to <4 x double>
+ %ve = fpext <4 x half> %splat to <4 x double>
+ %vf = fneg <4 x double> %va
+ %vg = fneg <4 x double> %vd
+ %vh = call <4 x double> @llvm.fma.v4f64(<4 x double> %vg, <4 x double> %ve, <4 x double> %vf)
+ ret <4 x double> %vh
+}
+
+define <4 x double> @vfwnmacc_fv_v4f64_v4f16(<4 x double> %va, <4 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmacc_fv_v4f64_v4f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vfmv.v.f v11, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v12, v10
+; CHECK-NEXT: vfwcvt.f.f.v v10, v11
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfwnmacc.vv v8, v12, v10
+; CHECK-NEXT: ret
+ %head = insertelement <4 x half> poison, half %c, i32 0
+ %splat = shufflevector <4 x half> %head, <4 x half> poison, <4 x i32> zeroinitializer
+ %vd = fpext <4 x half> %vb to <4 x double>
+ %ve = fpext <4 x half> %splat to <4 x double>
+ %vf = fneg <4 x double> %va
+ %vg = fneg <4 x double> %ve
+ %vh = call <4 x double> @llvm.fma.v4f64(<4 x double> %vd, <4 x double> %vg, <4 x double> %vf)
+ ret <4 x double> %vh
+}
+
+define <4 x double> @vfwmsac_vv_v4f64_v4f16(<4 x double> %va, <4 x half> %vb, <4 x half> %vc) {
+; CHECK-LABEL: vfwmsac_vv_v4f64_v4f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vfwcvt.f.f.v v12, v10
+; CHECK-NEXT: vfwcvt.f.f.v v10, v11
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfwmsac.vv v8, v12, v10
+; CHECK-NEXT: ret
+ %vd = fpext <4 x half> %vb to <4 x double>
+ %ve = fpext <4 x half> %vc to <4 x double>
+ %vf = fneg <4 x double> %va
+ %vg = call <4 x double> @llvm.fma.v4f64(<4 x double> %vd, <4 x double> %ve, <4 x double> %vf)
+ ret <4 x double> %vg
+}
+
+define <4 x double> @vfwmsac_vf_v4f64_v4f16(<4 x double> %va, <4 x half> %vb, half %c) {
+; CHECK-LABEL: vfwmsac_vf_v4f64_v4f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vfmv.v.f v11, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v12, v10
+; CHECK-NEXT: vfwcvt.f.f.v v10, v11
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfwmsac.vv v8, v12, v10
+; CHECK-NEXT: ret
+ %head = insertelement <4 x half> poison, half %c, i32 0
+ %splat = shufflevector <4 x half> %head, <4 x half> poison, <4 x i32> zeroinitializer
+ %vd = fpext <4 x half> %vb to <4 x double>
+ %ve = fpext <4 x half> %splat to <4 x double>
+ %vf = fneg <4 x double> %va
+ %vg = call <4 x double> @llvm.fma.v4f64(<4 x double> %vd, <4 x double> %ve, <4 x double> %vf)
+ ret <4 x double> %vg
+}
+
+define <4 x double> @vfwnmsac_vv_v4f64_v4f16(<4 x double> %va, <4 x half> %vb, <4 x half> %vc) {
+; CHECK-LABEL: vfwnmsac_vv_v4f64_v4f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vfwcvt.f.f.v v12, v10
+; CHECK-NEXT: vfwcvt.f.f.v v10, v11
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfwnmsac.vv v8, v12, v10
+; CHECK-NEXT: ret
+ %vd = fpext <4 x half> %vb to <4 x double>
+ %ve = fpext <4 x half> %vc to <4 x double>
+ %vf = fneg <4 x double> %vd
+ %vg = call <4 x double> @llvm.fma.v4f64(<4 x double> %vf, <4 x double> %ve, <4 x double> %va)
+ ret <4 x double> %vg
+}
+
+define <4 x double> @vfwnmsac_vf_v4f64_v4f16(<4 x double> %va, <4 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmsac_vf_v4f64_v4f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vfmv.v.f v11, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v12, v10
+; CHECK-NEXT: vfwcvt.f.f.v v10, v11
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfwnmsac.vv v8, v12, v10
+; CHECK-NEXT: ret
+ %head = insertelement <4 x half> poison, half %c, i32 0
+ %splat = shufflevector <4 x half> %head, <4 x half> poison, <4 x i32> zeroinitializer
+ %vd = fpext <4 x half> %vb to <4 x double>
+ %ve = fpext <4 x half> %splat to <4 x double>
+ %vf = fneg <4 x double> %vd
+ %vg = call <4 x double> @llvm.fma.v4f64(<4 x double> %vf, <4 x double> %ve, <4 x double> %va)
+ ret <4 x double> %vg
+}
+
+define <4 x double> @vfwnmsac_fv_v4f64_v4f16(<4 x double> %va, <4 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmsac_fv_v4f64_v4f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vfmv.v.f v11, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v12, v10
+; CHECK-NEXT: vfwcvt.f.f.v v10, v11
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfwnmsac.vv v8, v12, v10
+; CHECK-NEXT: ret
+ %head = insertelement <4 x half> poison, half %c, i32 0
+ %splat = shufflevector <4 x half> %head, <4 x half> poison, <4 x i32> zeroinitializer
+ %vd = fpext <4 x half> %vb to <4 x double>
+ %ve = fpext <4 x half> %splat to <4 x double>
+ %vf = fneg <4 x double> %ve
+ %vg = call <4 x double> @llvm.fma.v4f64(<4 x double> %vd, <4 x double> %vf, <4 x double> %va)
+ ret <4 x double> %vg
+}
+
+define <8 x double> @vfwmacc_vv_v8f64_v8f16(<8 x double> %va, <8 x half> %vb, <8 x half> %vc) {
+; CHECK-LABEL: vfwmacc_vv_v8f64_v8f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vfwcvt.f.f.v v14, v12
+; CHECK-NEXT: vfwcvt.f.f.v v16, v13
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vfwmacc.vv v8, v14, v16
+; CHECK-NEXT: ret
+ %vd = fpext <8 x half> %vb to <8 x double>
+ %ve = fpext <8 x half> %vc to <8 x double>
+ %vf = call <8 x double> @llvm.fma.v8f64(<8 x double> %vd, <8 x double> %ve, <8 x double> %va)
+ ret <8 x double> %vf
+}
+
+define <8 x double> @vfwmacc_vf_v8f64_v8f16(<8 x double> %va, <8 x half> %vb, half %c) {
+; CHECK-LABEL: vfwmacc_vf_v8f64_v8f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vfmv.v.f v13, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v14, v12
+; CHECK-NEXT: vfwcvt.f.f.v v16, v13
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vfwmacc.vv v8, v14, v16
+; CHECK-NEXT: ret
+ %head = insertelement <8 x half> poison, half %c, i32 0
+ %splat = shufflevector <8 x half> %head, <8 x half> poison, <8 x i32> zeroinitializer
+ %vd = fpext <8 x half> %vb to <8 x double>
+ %ve = fpext <8 x half> %splat to <8 x double>
+ %vf = call <8 x double> @llvm.fma.v8f64(<8 x double> %vd, <8 x double> %ve, <8 x double> %va)
+ ret <8 x double> %vf
+}
+
+define <8 x double> @vfwnmacc_vv_v8f64_v8f16(<8 x double> %va, <8 x half> %vb, <8 x half> %vc) {
+; CHECK-LABEL: vfwnmacc_vv_v8f64_v8f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vfwcvt.f.f.v v14, v12
+; CHECK-NEXT: vfwcvt.f.f.v v16, v13
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vfwnmacc.vv v8, v14, v16
+; CHECK-NEXT: ret
+ %vd = fpext <8 x half> %vb to <8 x double>
+ %ve = fpext <8 x half> %vc to <8 x double>
+ %vf = fneg <8 x double> %va
+ %vg = fneg <8 x double> %vd
+ %vh = call <8 x double> @llvm.fma.v8f64(<8 x double> %vg, <8 x double> %ve, <8 x double> %vf)
+ ret <8 x double> %vh
+}
+
+define <8 x double> @vfwnmacc_vf_v8f64_v8f16(<8 x double> %va, <8 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmacc_vf_v8f64_v8f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vfmv.v.f v13, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v14, v12
+; CHECK-NEXT: vfwcvt.f.f.v v16, v13
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vfwnmacc.vv v8, v14, v16
+; CHECK-NEXT: ret
+ %head = insertelement <8 x half> poison, half %c, i32 0
+ %splat = shufflevector <8 x half> %head, <8 x half> poison, <8 x i32> zeroinitializer
+ %vd = fpext <8 x half> %vb to <8 x double>
+ %ve = fpext <8 x half> %splat to <8 x double>
+ %vf = fneg <8 x double> %va
+ %vg = fneg <8 x double> %vd
+ %vh = call <8 x double> @llvm.fma.v8f64(<8 x double> %vg, <8 x double> %ve, <8 x double> %vf)
+ ret <8 x double> %vh
+}
+
+define <8 x double> @vfwnmacc_fv_v8f64_v8f16(<8 x double> %va, <8 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmacc_fv_v8f64_v8f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vfmv.v.f v13, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v14, v12
+; CHECK-NEXT: vfwcvt.f.f.v v16, v13
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vfwnmacc.vv v8, v14, v16
+; CHECK-NEXT: ret
+ %head = insertelement <8 x half> poison, half %c, i32 0
+ %splat = shufflevector <8 x half> %head, <8 x half> poison, <8 x i32> zeroinitializer
+ %vd = fpext <8 x half> %vb to <8 x double>
+ %ve = fpext <8 x half> %splat to <8 x double>
+ %vf = fneg <8 x double> %va
+ %vg = fneg <8 x double> %ve
+ %vh = call <8 x double> @llvm.fma.v8f64(<8 x double> %vd, <8 x double> %vg, <8 x double> %vf)
+ ret <8 x double> %vh
+}
+
+define <8 x double> @vfwmsac_vv_v8f64_v8f16(<8 x double> %va, <8 x half> %vb, <8 x half> %vc) {
+; CHECK-LABEL: vfwmsac_vv_v8f64_v8f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vfwcvt.f.f.v v14, v12
+; CHECK-NEXT: vfwcvt.f.f.v v16, v13
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vfwmsac.vv v8, v14, v16
+; CHECK-NEXT: ret
+ %vd = fpext <8 x half> %vb to <8 x double>
+ %ve = fpext <8 x half> %vc to <8 x double>
+ %vf = fneg <8 x double> %va
+ %vg = call <8 x double> @llvm.fma.v8f64(<8 x double> %vd, <8 x double> %ve, <8 x double> %vf)
+ ret <8 x double> %vg
+}
+
+define <8 x double> @vfwmsac_vf_v8f64_v8f16(<8 x double> %va, <8 x half> %vb, half %c) {
+; CHECK-LABEL: vfwmsac_vf_v8f64_v8f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vfmv.v.f v13, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v14, v12
+; CHECK-NEXT: vfwcvt.f.f.v v16, v13
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vfwmsac.vv v8, v14, v16
+; CHECK-NEXT: ret
+ %head = insertelement <8 x half> poison, half %c, i32 0
+ %splat = shufflevector <8 x half> %head, <8 x half> poison, <8 x i32> zeroinitializer
+ %vd = fpext <8 x half> %vb to <8 x double>
+ %ve = fpext <8 x half> %splat to <8 x double>
+ %vf = fneg <8 x double> %va
+ %vg = call <8 x double> @llvm.fma.v8f64(<8 x double> %vd, <8 x double> %ve, <8 x double> %vf)
+ ret <8 x double> %vg
+}
+
+define <8 x double> @vfwnmsac_vv_v8f64_v8f16(<8 x double> %va, <8 x half> %vb, <8 x half> %vc) {
+; CHECK-LABEL: vfwnmsac_vv_v8f64_v8f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vfwcvt.f.f.v v14, v12
+; CHECK-NEXT: vfwcvt.f.f.v v16, v13
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vfwnmsac.vv v8, v14, v16
+; CHECK-NEXT: ret
+ %vd = fpext <8 x half> %vb to <8 x double>
+ %ve = fpext <8 x half> %vc to <8 x double>
+ %vf = fneg <8 x double> %vd
+ %vg = call <8 x double> @llvm.fma.v8f64(<8 x double> %vf, <8 x double> %ve, <8 x double> %va)
+ ret <8 x double> %vg
+}
+
+define <8 x double> @vfwnmsac_vf_v8f64_v8f16(<8 x double> %va, <8 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmsac_vf_v8f64_v8f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vfmv.v.f v13, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v14, v12
+; CHECK-NEXT: vfwcvt.f.f.v v16, v13
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vfwnmsac.vv v8, v14, v16
+; CHECK-NEXT: ret
+ %head = insertelement <8 x half> poison, half %c, i32 0
+ %splat = shufflevector <8 x half> %head, <8 x half> poison, <8 x i32> zeroinitializer
+ %vd = fpext <8 x half> %vb to <8 x double>
+ %ve = fpext <8 x half> %splat to <8 x double>
+ %vf = fneg <8 x double> %vd
+ %vg = call <8 x double> @llvm.fma.v8f64(<8 x double> %vf, <8 x double> %ve, <8 x double> %va)
+ ret <8 x double> %vg
+}
+
+define <8 x double> @vfwnmsac_fv_v8f64_v8f16(<8 x double> %va, <8 x half> %vb, half %c) {
+; CHECK-LABEL: vfwnmsac_fv_v8f64_v8f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vfmv.v.f v13, fa0
+; CHECK-NEXT: vfwcvt.f.f.v v14, v12
+; CHECK-NEXT: vfwcvt.f.f.v v16, v13
+; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-NEXT: vfwnmsac.vv v8, v14, v16
+; CHECK-NEXT: ret
+ %head = insertelement <8 x half> poison, half %c, i32 0
+ %splat = shufflevector <8 x half> %head, <8 x half> poison, <8 x i32> zeroinitializer
+ %vd = fpext <8 x half> %vb to <8 x double>
+ %ve = fpext <8 x half> %splat to <8 x double>
+ %vf = fneg <8 x double> %ve
+ %vg = call <8 x double> @llvm.fma.v8f64(<8 x double> %vd, <8 x double> %vf, <8 x double> %va)
+ ret <8 x double> %vg
+}
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