[PATCH] D150527: [GlobalISel] Fix the erroneous transformation of BRCOND to BCC.

[hezuoqiang via Phabricator via llvm-commits]

hzq created this revision.
hzq added reviewers: paquette, kristof.beyls.
Herald added a subscriber: hiraditya.
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hzq requested review of this revision.
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https://reviews.llvm.org/D150527

Files:
  llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/speculative-hardening-brcond.mir


Index: llvm/test/CodeGen/AArch64/GlobalISel/speculative-hardening-brcond.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/speculative-hardening-brcond.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/speculative-hardening-brcond.mir
@@ -21,7 +21,7 @@
   ; CHECK:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
   ; CHECK:   %reg:gpr32 = COPY $w0
   ; CHECK:   [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg, 1, implicit-def $nzcv
-  ; CHECK:   Bcc 0, %bb.1, implicit $nzcv
+  ; CHECK:   Bcc 1, %bb.1, implicit $nzcv
   ; CHECK:   B %bb.0
   ; CHECK: bb.1:
   ; CHECK:   RET_ReallyLR
Index: llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
===================================================================
--- llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -1774,7 +1774,7 @@
       MIB.buildInstr(AArch64::ANDSWri, {LLT::scalar(32)}, {CondReg}).addImm(1);
   constrainSelectedInstRegOperands(*TstMI, TII, TRI, RBI);
   auto Bcc = MIB.buildInstr(AArch64::Bcc)
-                 .addImm(AArch64CC::EQ)
+                 .addImm(AArch64CC::NE)
                  .addMBB(I.getOperand(1).getMBB());
   I.eraseFromParent();
   return constrainSelectedInstRegOperands(*Bcc, TII, TRI, RBI);


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