[llvm] e36caae - [SelectionDAG] Use `computeKnownBits` if `Op` is not recognized by `isKnownNeverZero`

[Noah Goldstein via llvm-commits]

Author: Noah Goldstein
Date: 2023-05-13T14:36:04-05:00
New Revision: e36caaeeb25fafba0851e4a1905c7ceb08c337a8

URL: https://github.com/llvm/llvm-project/commit/e36caaeeb25fafba0851e4a1905c7ceb08c337a8
DIFF: https://github.com/llvm/llvm-project/commit/e36caaeeb25fafba0851e4a1905c7ceb08c337a8.diff

LOG: [SelectionDAG] Use `computeKnownBits` if `Op` is not recognized by `isKnownNeverZero`

The current logic is pretty limitted unless the `Op` is a
constant. This at least covers more obvious cases.

Reviewed By: craig.topper, foad

Differential Revision: https://reviews.llvm.org/D149196

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/test/CodeGen/ARM/cttz_vector.ll

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index b46ca15233d3..e447963f23c9 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5064,7 +5064,7 @@ bool SelectionDAG::isKnownNeverZero(SDValue Op, unsigned Depth) const {
     break;
   }
 
-  return false;
+  return computeKnownBits(Op, Depth).isNonZero();
 }
 
 bool SelectionDAG::isEqualTo(SDValue A, SDValue B) const {

diff  --git a/llvm/test/CodeGen/ARM/cttz_vector.ll b/llvm/test/CodeGen/ARM/cttz_vector.ll
index a68b0b529cdf..988ea5d4acb1 100644
--- a/llvm/test/CodeGen/ARM/cttz_vector.ll
+++ b/llvm/test/CodeGen/ARM/cttz_vector.ll
@@ -65,14 +65,13 @@ define void @test_v4i8(ptr %p) {
 ; CHECK-LABEL: test_v4i8:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vld1.32 {d16[0]}, [r0:32]
-; CHECK-NEXT:    vmov.i16 d19, #0x1
 ; CHECK-NEXT:    vmovl.u8 q8, d16
 ; CHECK-NEXT:    vorr.i16 d16, #0x100
 ; CHECK-NEXT:    vneg.s16 d18, d16
 ; CHECK-NEXT:    vand d16, d16, d18
-; CHECK-NEXT:    vsub.i16 d16, d16, d19
-; CHECK-NEXT:    vcnt.8 d16, d16
-; CHECK-NEXT:    vpaddl.u8 d16, d16
+; CHECK-NEXT:    vmov.i16 d17, #0xf
+; CHECK-NEXT:    vclz.i16 d16, d16
+; CHECK-NEXT:    vsub.i16 d16, d17, d16
 ; CHECK-NEXT:    vuzp.8 d16, d17
 ; CHECK-NEXT:    vst1.32 {d16[0]}, [r0:32]
 ; CHECK-NEXT:    bx lr