[PATCH] D150098: [DAGCombiner] Improve `computeKnownBits` implementations of `sdiv` and `udiv`

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n added inline comments.


================
Comment at: llvm/test/CodeGen/ARM/select-imm.ll:660
 ; V8MBASE-NEXT:    str r0, [sp]
-; V8MBASE-NEXT:    adds r0, r0, #5
-; V8MBASE-NEXT:    str r0, [sp, #4]
-; V8MBASE-NEXT:    movs r1, #0
+; V8MBASE-NEXT:    adds r1, r0, #5
+; V8MBASE-NEXT:    str r1, [sp, #4]
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goldstein.w.n wrote:
> @rksimon this ends up causing a regression. Had only run x86 backend tests by mistake earlier. @t.p.northover is this acceptable for you guys? The change here is just adding more information to `computeKnownBits` so a regression in ARM backend likely means there is buggy/flakey fold.
I'm going to assume this is okay. The middle end would never produce the IR (it constant evaluates to `true`).


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150098/new/

https://reviews.llvm.org/D150098