[llvm] 5d57a9f - [PowerPC] Adjust tests after e351b9b66da088.
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Fri May 12 12:20:29 PDT 2023
Author: Florian Hahn
Date: 2023-05-12T20:20:13+01:00
New Revision: 5d57a9fd2b9b4905b5845f6df6eb09bf08c8a4c6
URL: https://github.com/llvm/llvm-project/commit/5d57a9fd2b9b4905b5845f6df6eb09bf08c8a4c6
DIFF: https://github.com/llvm/llvm-project/commit/5d57a9fd2b9b4905b5845f6df6eb09bf08c8a4c6.diff
LOG: [PowerPC] Adjust tests after e351b9b66da088.
Those tests were missed when landing e351b9b66da088.
Added:
Modified:
llvm/test/CodeGen/PowerPC/expand-foldable-isel.ll
llvm/test/CodeGen/PowerPC/loop-instr-form-non-inc.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/PowerPC/expand-foldable-isel.ll b/llvm/test/CodeGen/PowerPC/expand-foldable-isel.ll
index b50138a936d50..8f671bc9bfe01 100644
--- a/llvm/test/CodeGen/PowerPC/expand-foldable-isel.ll
+++ b/llvm/test/CodeGen/PowerPC/expand-foldable-isel.ll
@@ -36,24 +36,29 @@ define void @_ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot
; CHECK-GEN-ISEL-TRUE-NEXT: # implicit-def: $x3
; CHECK-GEN-ISEL-TRUE-NEXT: # implicit-def: $r29
; CHECK-GEN-ISEL-TRUE-NEXT: std r0, 80(r1)
+; CHECK-GEN-ISEL-TRUE-NEXT: b .LBB0_2
; CHECK-GEN-ISEL-TRUE-NEXT: .p2align 4
-; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_1: # %while.cond11
+; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_1: # %cond.false21.i156
+; CHECK-GEN-ISEL-TRUE-NEXT: #
+; CHECK-GEN-ISEL-TRUE-NEXT: addi r4, r29, 1
+; CHECK-GEN-ISEL-TRUE-NEXT: srawi r4, r4, 1
+; CHECK-GEN-ISEL-TRUE-NEXT: addze r29, r4
+; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_2: # %while.cond11
; CHECK-GEN-ISEL-TRUE-NEXT: #
; CHECK-GEN-ISEL-TRUE-NEXT: lwz r4, 0(r3)
; CHECK-GEN-ISEL-TRUE-NEXT: cmplwi r4, 0
-; CHECK-GEN-ISEL-TRUE-NEXT: beq cr0, .LBB0_3
-; CHECK-GEN-ISEL-TRUE-NEXT: # %bb.2: # %while.body21
+; CHECK-GEN-ISEL-TRUE-NEXT: beq cr0, .LBB0_5
+; CHECK-GEN-ISEL-TRUE-NEXT: # %bb.3: # %while.body21
; CHECK-GEN-ISEL-TRUE-NEXT: #
; CHECK-GEN-ISEL-TRUE-NEXT: bl ZN3pov10pov_callocEmmPKciS1_pov
; CHECK-GEN-ISEL-TRUE-NEXT: nop
-; CHECK-GEN-ISEL-TRUE-NEXT: addi r4, r29, 1
-; CHECK-GEN-ISEL-TRUE-NEXT: srwi r5, r29, 1
-; CHECK-GEN-ISEL-TRUE-NEXT: srawi r4, r4, 1
; CHECK-GEN-ISEL-TRUE-NEXT: std r3, 0(r3)
-; CHECK-GEN-ISEL-TRUE-NEXT: addze r4, r4
-; CHECK-GEN-ISEL-TRUE-NEXT: isel r29, r4, r5, 4*cr5+lt
-; CHECK-GEN-ISEL-TRUE-NEXT: b .LBB0_1
-; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_3: # %lor.rhs
+; CHECK-GEN-ISEL-TRUE-NEXT: bc 12, 4*cr5+lt, .LBB0_1
+; CHECK-GEN-ISEL-TRUE-NEXT: # %bb.4: # %cond.true18.i153
+; CHECK-GEN-ISEL-TRUE-NEXT: #
+; CHECK-GEN-ISEL-TRUE-NEXT: srwi r29, r29, 1
+; CHECK-GEN-ISEL-TRUE-NEXT: b .LBB0_2
+; CHECK-GEN-ISEL-TRUE-NEXT: .LBB0_5: # %lor.rhs
; CHECK-GEN-ISEL-TRUE-NEXT: std r30, 16(r3)
; CHECK-GEN-ISEL-TRUE-NEXT: addi r1, r1, 64
; CHECK-GEN-ISEL-TRUE-NEXT: ld r0, 16(r1)
@@ -76,33 +81,29 @@ define void @_ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot
; CHECK-NEXT: # implicit-def: $x3
; CHECK-NEXT: # implicit-def: $r29
; CHECK-NEXT: std r0, 80(r1)
+; CHECK-NEXT: b .LBB0_2
; CHECK-NEXT: .p2align 4
-; CHECK-NEXT: .LBB0_1: # %while.cond11
+; CHECK-NEXT: .LBB0_1: # %cond.false21.i156
+; CHECK-NEXT: #
+; CHECK-NEXT: addi r4, r29, 1
+; CHECK-NEXT: srawi r4, r4, 1
+; CHECK-NEXT: addze r29, r4
+; CHECK-NEXT: .LBB0_2: # %while.cond11
; CHECK-NEXT: #
; CHECK-NEXT: lwz r4, 0(r3)
; CHECK-NEXT: cmplwi r4, 0
-; CHECK-NEXT: beq cr0, .LBB0_6
-; CHECK-NEXT: # %bb.2: # %while.body21
+; CHECK-NEXT: beq cr0, .LBB0_5
+; CHECK-NEXT: # %bb.3: # %while.body21
; CHECK-NEXT: #
; CHECK-NEXT: bl ZN3pov10pov_callocEmmPKciS1_pov
; CHECK-NEXT: nop
-; CHECK-NEXT: addi r4, r29, 1
-; CHECK-NEXT: srwi r5, r29, 1
-; CHECK-NEXT: srawi r4, r4, 1
; CHECK-NEXT: std r3, 0(r3)
-; CHECK-NEXT: addze r4, r4
-; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_4
-; CHECK-NEXT: # %bb.3: # %while.body21
-; CHECK-NEXT: #
-; CHECK-NEXT: ori r29, r5, 0
-; CHECK-NEXT: b .LBB0_5
-; CHECK-NEXT: .LBB0_4: # %while.body21
-; CHECK-NEXT: #
-; CHECK-NEXT: addi r29, r4, 0
-; CHECK-NEXT: .LBB0_5: # %while.body21
+; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_1
+; CHECK-NEXT: # %bb.4: # %cond.true18.i153
; CHECK-NEXT: #
-; CHECK-NEXT: b .LBB0_1
-; CHECK-NEXT: .LBB0_6: # %lor.rhs
+; CHECK-NEXT: srwi r29, r29, 1
+; CHECK-NEXT: b .LBB0_2
+; CHECK-NEXT: .LBB0_5: # %lor.rhs
; CHECK-NEXT: std r30, 16(r3)
; CHECK-NEXT: addi r1, r1, 64
; CHECK-NEXT: ld r0, 16(r1)
diff --git a/llvm/test/CodeGen/PowerPC/loop-instr-form-non-inc.ll b/llvm/test/CodeGen/PowerPC/loop-instr-form-non-inc.ll
index 93697ec06be2c..e87d6392c4c7b 100644
--- a/llvm/test/CodeGen/PowerPC/loop-instr-form-non-inc.ll
+++ b/llvm/test/CodeGen/PowerPC/loop-instr-form-non-inc.ll
@@ -11,13 +11,18 @@ define dso_local void @test_no_inc(i32 signext %a) local_unnamed_addr nounwind a
; CHECK-NEXT: li 7, 0
; CHECK-NEXT: andc 4, 3, 4
; CHECK-NEXT: addi 5, 4, 1
+; CHECK-NEXT: b .LBB0_2
; CHECK-NEXT: .p2align 5
-; CHECK-NEXT: .LBB0_1: # %for.cond
+; CHECK-NEXT: .LBB0_1: # %for.cond.cleanup
; CHECK-NEXT: #
-; CHECK-NEXT: add 8, 3, 6
; CHECK-NEXT: stb 7, 0(5)
; CHECK-NEXT: add 5, 5, 4
-; CHECK-NEXT: iselgt 6, 8, 6
+; CHECK-NEXT: .LBB0_2: # %for.cond
+; CHECK-NEXT: #
+; CHECK-NEXT: bc 4, 1, .LBB0_1
+; CHECK-NEXT: # %bb.3: # %for.body.preheader
+; CHECK-NEXT: #
+; CHECK-NEXT: add 6, 3, 6
; CHECK-NEXT: b .LBB0_1
entry:
%cmp10 = icmp sgt i32 %a, 0
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