[PATCH] D149743: [RISCV][CodeGen] Support Zdinx on RV32 codegen

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:350
+          .addImm(MBBI->getOperand(2).getImm());
+      BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), TmpReg)
+          .addReg(TmpReg)
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jrtc27 wrote:
> StephenFan wrote:
> > if MBBI->getOperand(1).isKill() is true, maybe we don't need to add back -4?
> This is just silly; expand it during ISel and let the register allocator figure out if it can reuse the register or needs to allocate an extra one
Also surely that would let the existing peephole passes work on optimising the simple expanded form into the more compact form when the immediate fits?


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https://reviews.llvm.org/D149743