[PATCH] D150316: [AArch64][InstCombine] Don't scalarize for bitselet instructions

[Pranav Kant via Phabricator via llvm-commits]

pranavk added a comment.

I agree that it's not ideal to have target-specific logic in this file.

Current InstCombine implementation is too simple and uses cheapToScalarize function to find if it should scalarize the IR. This function (cheapToScalarize) recursively calls itself until it finds one of the operands that's really cheap to scalarize. The problem is that it returns true for whole instruction DAG. That's what's happening here as well. Recursion reaches Xor (A, {-1, -1, -1, -1}) which looks at {-1, -1, -1, -1} and immediately concludes that whole Instruction DAG is cheap to scalarize.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D150316/new/

https://reviews.llvm.org/D150316