[PATCH] D149743: [RISCV][CodeGen] Support Zdinx on RV32 codegen

[luxufan via Phabricator via llvm-commits]

StephenFan added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:288
+  } else {
+    if (MBBI->getOperand(2).getImm() < 0X7FC) {
+      BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
----------------



================
Comment at: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:350
+          .addImm(MBBI->getOperand(2).getImm());
+      BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), TmpReg)
+          .addReg(TmpReg)
----------------
if MBBI->getOperand(1).isKill() is true, maybe we don't need to add back -4?


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https://reviews.llvm.org/D149743