[PATCH] D105889: [AArch64][SVE] Break false dependencies for inactive lanes of unary operations

Thu May 11 19:42:06 PDT 2023

TiehuZhang added a comment.

In D105889#4334504 <https://reviews.llvm.org/D105889#4334504>, @paulwalker-arm wrote:

> In D105889#4323865 <https://reviews.llvm.org/D105889#4323865>, @TiehuZhang wrote:
>
>> Hi, @bsmith, sorry to bother you, could you tell me the background of the patch? 
>> I have a question about the patch, as I notice that the patch adds `movprfx` before some instructions, and the optimization may affect the performance(degradation).
>> ; CHECK-NEXT:    ptrue p0.d
>> +**; CHECK-NEXT:    movprfx z0, z1**
>> ; CHECK-NEXT:    fsqrt z0.d, p0/m, z1.d
>
> The rational for the patch is to ensure the inactive lanes of unary operations don't have a dependence on  previous operations when the results for inactive lanes is not important (i.e. undef).  Taking the above example, the problem with not breaking the dependency is that if z0.d is used as the result for a preceding long latency instruction then it can negatively impact the issue latency of this instructions despite there being no "real" dependency.
>
> For this reason it is preferred to always break such dependencies via a `movprfx` instruction.  The intent here is that `movprfx` is suppose to be free because the architecture prefers implementations to combine movprfx'd destructive instructions into constructive instructions. However, we are aware of issues where register allocation is making some poor decisions that is leading to `movprfx` being over used because dedicated destination registers are being allocated even though it would be advantageous to reuse an operand register.

I got it, thanks for your reply!

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