[llvm] c2ce2a5 - [LoongArch] clang-format LoongArchISelLowering.cpp. NFC
Weining Lu via llvm-commits
llvm-commits at lists.llvm.org
Thu May 11 19:12:17 PDT 2023
Author: Weining Lu
Date: 2023-05-12T10:11:12+08:00
New Revision: c2ce2a509f74a85a3c0ef4b9d6d79fbacc7e8bdf
URL: https://github.com/llvm/llvm-project/commit/c2ce2a509f74a85a3c0ef4b9d6d79fbacc7e8bdf
DIFF: https://github.com/llvm/llvm-project/commit/c2ce2a509f74a85a3c0ef4b9d6d79fbacc7e8bdf.diff
LOG: [LoongArch] clang-format LoongArchISelLowering.cpp. NFC
Added:
Modified:
llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index a8c4dc4762ee5..6bf7e1a4b63d1 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -34,10 +34,9 @@ using namespace llvm;
STATISTIC(NumTailCalls, "Number of tail calls");
-static cl::opt<bool> ZeroDivCheck(
- "loongarch-check-zero-division", cl::Hidden,
- cl::desc("Trap on integer division by zero."),
- cl::init(false));
+static cl::opt<bool> ZeroDivCheck("loongarch-check-zero-division", cl::Hidden,
+ cl::desc("Trap on integer division by zero."),
+ cl::init(false));
LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
const LoongArchSubtarget &STI)
@@ -2070,8 +2069,8 @@ void LoongArchTargetLowering::analyzeInputArgs(
MF.getSubtarget<LoongArchSubtarget>().getTargetABI();
if (Fn(MF.getDataLayout(), ABI, i, ArgVT, CCValAssign::Full, Ins[i].Flags,
CCInfo, /*IsFixed=*/true, IsRet, ArgTy)) {
- LLVM_DEBUG(dbgs() << "InputArg #" << i << " has unhandled type "
- << ArgVT << '\n');
+ LLVM_DEBUG(dbgs() << "InputArg #" << i << " has unhandled type " << ArgVT
+ << '\n');
llvm_unreachable("");
}
}
@@ -2088,8 +2087,8 @@ void LoongArchTargetLowering::analyzeOutputArgs(
MF.getSubtarget<LoongArchSubtarget>().getTargetABI();
if (Fn(MF.getDataLayout(), ABI, i, ArgVT, CCValAssign::Full, Outs[i].Flags,
CCInfo, Outs[i].IsFixed, IsRet, OrigTy)) {
- LLVM_DEBUG(dbgs() << "OutputArg #" << i << " has unhandled type "
- << ArgVT << "\n");
+ LLVM_DEBUG(dbgs() << "OutputArg #" << i << " has unhandled type " << ArgVT
+ << "\n");
llvm_unreachable("");
}
}
@@ -2177,14 +2176,15 @@ static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDValue Val,
}
static bool CC_LoongArch_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
- CCValAssign::LocInfo LocInfo,
- ISD::ArgFlagsTy ArgFlags, CCState &State) {
+ CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
if (LocVT == MVT::i32 || LocVT == MVT::i64) {
// Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, SpLim
// s0 s1 s2 s3 s4 s5 s6 s7 s8
static const MCPhysReg GPRList[] = {
- LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27,
- LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31};
+ LoongArch::R23, LoongArch::R24, LoongArch::R25,
+ LoongArch::R26, LoongArch::R27, LoongArch::R28,
+ LoongArch::R29, LoongArch::R30, LoongArch::R31};
if (unsigned Reg = State.AllocateReg(GPRList)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
@@ -2235,7 +2235,7 @@ SDValue LoongArchTargetLowering::LowerFormalArguments(
if (!MF.getSubtarget().hasFeature(LoongArch::FeatureBasicF) ||
!MF.getSubtarget().hasFeature(LoongArch::FeatureBasicD))
report_fatal_error(
- "GHC calling convention requires the F and D extensions");
+ "GHC calling convention requires the F and D extensions");
}
EVT PtrVT = getPointerTy(DAG.getDataLayout());
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