[PATCH] D150398: [VPlan] Model branch cond to enter scalar epilogue in VPlan.

[Florian Hahn via Phabricator via llvm-commits]

fhahn created this revision.
fhahn added reviewers: Ayal, gilr, rengolin.
Herald added subscribers: StephenFan, tschuett, psnobl, rogfer01, bollu, hiraditya.
Herald added a project: All.
fhahn requested review of this revision.
Herald added subscribers: pcwang-thead, vkmr.
Herald added a project: LLVM.

This patch moves branch condition creation to enter the scalar epilogue
loop to VPlan. It introduces a new ICmpEQ opcode to VPInstruction and a
new live-out that just updates the branch condition with a given value.
This requires introducing subclassess for VPLiveOut.

For now this is still WIP as the ICmpEQ codegen isn't general yet and
most VPlan printing tests need updating. I'll do that once we converge
on the overall design. Also currently we keep all live-outs in a map
with phi nodes, which doesn't make sense for the new live-out.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D150398

Files:
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
  llvm/lib/Transforms/Vectorize/VPlan.cpp
  llvm/lib/Transforms/Vectorize/VPlan.h
  llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
  llvm/lib/Transforms/Vectorize/VPlanValue.h
  llvm/test/Transforms/LoopVectorize/pr59319-loop-access-info-invalidation.ll
  llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll

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