[PATCH] D149743: [RISCV][CodeGen] Support Zdinx on RV32 codegen

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:302
+      BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), Lo)
+          .addReg(MBBI->getOperand(1).getReg(),
+                  getKillRegState(MBBI->getOperand(1).isKill()))
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Doesn't this need to use Lo as its input?


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Comment at: llvm/test/CodeGen/RISCV/zdinx-rv32.ll:17
+; RV32ZDINX-NEXT:    sw a3, 2044(a2)
+; RV32ZDINX-NEXT:    addi a2, a0, -4
+; RV32ZDINX-NEXT:    addi sp, sp, 16
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As I noted in the source code, this should be `addi a2, a2, -4`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149743/new/

https://reviews.llvm.org/D149743