[llvm] d262a11 - [NFC][AMDGPU] Pre-commit test.

[Thomas Symalla via llvm-commits]

Author: Thomas Symalla
Date: 2023-05-11T09:44:12+02:00
New Revision: d262a11a38b172bc9b538af571eae69b1e5c4c70

URL: https://github.com/llvm/llvm-project/commit/d262a11a38b172bc9b538af571eae69b1e5c4c70
DIFF: https://github.com/llvm/llvm-project/commit/d262a11a38b172bc9b538af571eae69b1e5c4c70.diff

LOG: [NFC][AMDGPU] Pre-commit test.

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/fold-fabs.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AMDGPU/fold-fabs.ll b/llvm/test/CodeGen/AMDGPU/fold-fabs.ll
index cd3cbb414e8d..95b5e3828e86 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-fabs.ll
+++ b/llvm/test/CodeGen/AMDGPU/fold-fabs.ll
@@ -34,6 +34,43 @@ exit:
   ret float %ret
 }
 
+define float @fold_abs_in_branch_multiple_users(float %arg1, float %arg2) {
+; GFX10-LABEL: fold_abs_in_branch_multiple_users:
+; GFX10:       ; %bb.0: ; %entry
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_add_f32_e32 v0, v0, v1
+; GFX10-NEXT:    s_mov_b32 s4, exec_lo
+; GFX10-NEXT:    v_add_f32_e32 v1, v0, v1
+; GFX10-NEXT:    v_add_f32_e64 v0, |v1|, |v1|
+; GFX10-NEXT:    v_and_b32_e32 v1, 0x7fffffff, v1
+; GFX10-NEXT:    v_cmpx_nlt_f32_e32 1.0, v0
+; GFX10-NEXT:  ; %bb.1: ; %if
+; GFX10-NEXT:    v_mul_f32_e32 v0, 0x3e4ccccd, v1
+; GFX10-NEXT:  ; %bb.2: ; %exit
+; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s4
+; GFX10-NEXT:    v_add_f32_e32 v1, 2.0, v1
+; GFX10-NEXT:    v_mul_f32_e32 v0, v1, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+entry:
+  %0 = fadd reassoc nnan nsz arcp contract afn float %arg1, %arg2
+  %1 = fadd reassoc nnan nsz arcp contract afn float %0, %arg2
+  %2 = call reassoc nnan nsz arcp contract afn float @llvm.fabs.f32(float %1)
+  %3 = fmul reassoc nnan nsz arcp contract afn float %2, 2.000000e+00
+  %4 = fcmp ule float %3, 1.000000e+00
+  br i1 %4, label %if, label %exit
+
+if:
+  %if.3 = fmul reassoc nnan nsz arcp contract afn float %2, 0x3FC99999A0000000
+  br label %exit
+
+exit:
+  %exit.phi = phi float [ %3, %entry ], [ %if.3, %if ]
+  %ret.0 = fadd reassoc nnan nsz arcp contract afn float %2, 2.000000e+00
+  %ret.1 = fmul float %ret.0, %exit.phi
+  ret float %ret.1
+}
+
 define float @fold_abs_in_branch_undef(float %arg1, float %arg2) {
 ; GFX10-LABEL: fold_abs_in_branch_undef:
 ; GFX10:       ; %bb.0: ; %entry
@@ -42,10 +79,10 @@ define float @fold_abs_in_branch_undef(float %arg1, float %arg2) {
 ; GFX10-NEXT:    v_add_f32_e64 v0, |s4|, |s4|
 ; GFX10-NEXT:    s_bitset0_b32 s4, 31
 ; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, 1.0, v0
-; GFX10-NEXT:    s_cbranch_vccnz .LBB1_2
+; GFX10-NEXT:    s_cbranch_vccnz .LBB2_2
 ; GFX10-NEXT:  ; %bb.1: ; %if
 ; GFX10-NEXT:    v_mul_f32_e64 v0, 0x3e4ccccd, s4
-; GFX10-NEXT:  .LBB1_2: ; %exit
+; GFX10-NEXT:  .LBB2_2: ; %exit
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %0 = fadd reassoc nnan nsz arcp contract afn float %arg1, %arg2
@@ -72,10 +109,10 @@ define float @fold_abs_in_branch_poison(float %arg1, float %arg2) {
 ; GFX10-NEXT:    v_add_f32_e64 v0, |s4|, |s4|
 ; GFX10-NEXT:    s_bitset0_b32 s4, 31
 ; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, 1.0, v0
-; GFX10-NEXT:    s_cbranch_vccnz .LBB2_2
+; GFX10-NEXT:    s_cbranch_vccnz .LBB3_2
 ; GFX10-NEXT:  ; %bb.1: ; %if
 ; GFX10-NEXT:    v_mul_f32_e64 v0, 0x3e4ccccd, s4
-; GFX10-NEXT:  .LBB2_2: ; %exit
+; GFX10-NEXT:  .LBB3_2: ; %exit
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 entry:
   %0 = fadd reassoc nnan nsz arcp contract afn float %arg1, %arg2
@@ -138,14 +175,14 @@ define float @fold_abs_in_branch_phi(float %arg1, float %arg2) {
 ; GFX10-NEXT:    v_add_f32_e32 v0, v0, v1
 ; GFX10-NEXT:    v_add_f32_e64 v0, |v0|, |v0|
 ; GFX10-NEXT:    v_cmpx_nlt_f32_e32 1.0, v0
-; GFX10-NEXT:    s_cbranch_execz .LBB4_2
-; GFX10-NEXT:  .LBB4_1: ; %l
+; GFX10-NEXT:    s_cbranch_execz .LBB5_2
+; GFX10-NEXT:  .LBB5_1: ; %l
 ; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; GFX10-NEXT:    v_mul_f32_e32 v0, 0x40400000, v0
 ; GFX10-NEXT:    v_cmp_lt_f32_e32 vcc_lo, -1.0, v0
 ; GFX10-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
-; GFX10-NEXT:    s_cbranch_vccnz .LBB4_1
-; GFX10-NEXT:  .LBB4_2: ; %exit
+; GFX10-NEXT:    s_cbranch_vccnz .LBB5_1
+; GFX10-NEXT:  .LBB5_2: ; %exit
 ; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 entry: