[PATCH] D150324: [X86] Make constant `mul` -> `shl` + `add`/`sub` work for vector types

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

On current chips, pmullw has the same throughput as psllw; it seems unlikely to me that it's profitable to replace a pmullw with a four-instruction sequence.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D150324/new/

https://reviews.llvm.org/D150324