[PATCH] D148834: [RISCV][InsertVSETVLI] Avoid VL toggles for extractelement patterns

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

In D148834#4331814 <https://reviews.llvm.org/D148834#4331814>, @rogfer01 wrote:

> Can anyone else reproduce this?

I think this is now fixed, but my cross build environment for test-suite is a giant collection of hacks.  Confirmation that this now works end to end would be appreciated.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148834/new/

https://reviews.llvm.org/D148834