[llvm] 020812b - Reapply "[RISCV][InsertVSETVLI] Avoid VL toggles for extractelement patterns"
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Wed May 10 11:52:04 PDT 2023
Author: Philip Reames
Date: 2023-05-10T11:51:51-07:00
New Revision: 020812b64f2338a0e96d6d2a358d075bf942986f
URL: https://github.com/llvm/llvm-project/commit/020812b64f2338a0e96d6d2a358d075bf942986f
DIFF: https://github.com/llvm/llvm-project/commit/020812b64f2338a0e96d6d2a358d075bf942986f.diff
LOG: Reapply "[RISCV][InsertVSETVLI] Avoid VL toggles for extractelement patterns"
The original change had a bug where it allowed SEW mutation. This is wrong in multiple ways, but an easy example is that the slide amount is in units of SEW, and thus that changing SEW changes the slide offset.
I'd reverted this in 33314693 intending to more majorly rework the patch because in addition to the bug, I'd noticed a potential oppurtunity to increase scope. After implementing that variant, and realizing it triggered nowhere, I decided to go back to the prior patch with the minimal fix.
Note there's no separate test case for the fix. This is because we already had multiple, and I just didn't realize the impact of the original test diff. Adding one more test would have been unlikely to catch that human error.
Original commit message..
Noticed this while looking at some SLP output. If we have an extractelement, we're probably using a slidedown into an destination with no contents. Given this, we can allow the slideup to use a larger VL and clobber tail elements of the destination vector. Doing this allows us to avoid vsetvli toggles in many fixed length vector examples.
Differential Revision: https://reviews.llvm.org/D148834
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
llvm/test/CodeGen/RISCV/rvv/fold-vector-cmp.ll
llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll
llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 76d0974e7037..9040427106ee 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -85,6 +85,18 @@ static bool isScalarMoveInstr(const MachineInstr &MI) {
}
}
+static bool isVSlideInstr(const MachineInstr &MI) {
+ switch (getRVVMCOpcode(MI.getOpcode())) {
+ default:
+ return false;
+ case RISCV::VSLIDEDOWN_VX:
+ case RISCV::VSLIDEDOWN_VI:
+ case RISCV::VSLIDEUP_VX:
+ case RISCV::VSLIDEUP_VI:
+ return true;
+ }
+}
+
/// Get the EEW for a load or store instruction. Return std::nullopt if MI is
/// not a load or store which ignores SEW.
static std::optional<unsigned> getEEWForLoadStore(const MachineInstr &MI) {
@@ -818,6 +830,11 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
.addImm(Info.encodeVTYPE());
}
+static bool isLMUL1OrSmaller(RISCVII::VLMUL LMUL) {
+ auto [LMul, Fractional] = RISCVVType::decodeVLMUL(LMUL);
+ return Fractional || LMul == 1;
+}
+
/// Return true if a VSETVLI is required to transition from CurInfo to Require
/// before MI.
bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI,
@@ -845,6 +862,25 @@ bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI,
}
}
+ // A slidedown/slideup with an IMPLICIT_DEF merge op can freely clobber
+ // elements not copied from the source vector (e.g. masked off, tail, or
+ // slideup's prefix). Notes:
+ // * We can't modify SEW here since the slide amount is in units of SEW.
+ // * VL=1 is special only because we have existing support for zero vs
+ // non-zero VL. We could generalize this if we had a VL > C predicate.
+ // * The LMUL1 restriction is for machines whose latency may depend on VL.
+ // * As above, this is only legal for IMPLICIT_DEF, not TA.
+ if (isVSlideInstr(MI) && Require.hasAVLImm() && Require.getAVLImm() == 1 &&
+ isLMUL1OrSmaller(CurInfo.getVLMUL())) {
+ auto *VRegDef = MRI->getVRegDef(MI.getOperand(1).getReg());
+ if (VRegDef && VRegDef->isImplicitDef()) {
+ Used.VLAny = false;
+ Used.VLZeroness = true;
+ Used.LMUL = false;
+ Used.TailPolicy = false;
+ }
+ }
+
if (CurInfo.isCompatible(Used, Require))
return false;
diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
index 353f8119bd33..2210ed4720c5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
@@ -10,7 +10,6 @@ define i1 @extractelt_nxv1i1(<vscale x 1 x i8>* %x, i64 %idx) nounwind {
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
@@ -28,7 +27,6 @@ define i1 @extractelt_nxv2i1(<vscale x 2 x i8>* %x, i64 %idx) nounwind {
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
@@ -46,7 +44,6 @@ define i1 @extractelt_nxv4i1(<vscale x 4 x i8>* %x, i64 %idx) nounwind {
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
@@ -64,7 +61,6 @@ define i1 @extractelt_nxv8i1(<vscale x 8 x i8>* %x, i64 %idx) nounwind {
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll
index dd5921313e61..99d7b4963db7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll
@@ -16,9 +16,7 @@ define <2 x i1> @reverse_v2i1(<2 x i1> %a) {
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
-; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vmsne.vi v0, v9, 0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
index 6bde962dac0a..2ee0e44253d6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
@@ -30,7 +30,6 @@ define i1 @extractelt_v2i1(ptr %x, i64 %idx) nounwind {
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
@@ -48,7 +47,6 @@ define i1 @extractelt_v4i1(ptr %x, i64 %idx) nounwind {
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
index b860916a3adf..16c7611a8443 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
@@ -9,7 +9,6 @@ define i8 @extractelt_v16i8(ptr %x) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
-; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 7
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
@@ -23,7 +22,6 @@ define i16 @extractelt_v8i16(ptr %x) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 7
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
@@ -37,7 +35,6 @@ define i32 @extractelt_v4i32(ptr %x) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
@@ -74,7 +71,6 @@ define half @extractelt_v8f16(ptr %x) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 7
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@@ -88,7 +84,6 @@ define float @extractelt_v4f32(ptr %x) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@@ -252,7 +247,6 @@ define i8 @extractelt_v16i8_idx(ptr %x, i32 zeroext %idx) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
-; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
@@ -266,7 +260,6 @@ define i16 @extractelt_v8i16_idx(ptr %x, i32 zeroext %idx) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
@@ -281,7 +274,6 @@ define i32 @extractelt_v4i32_idx(ptr %x, i32 zeroext %idx) nounwind {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vadd.vv v8, v8, v8
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
@@ -297,10 +289,10 @@ define i64 @extractelt_v2i64_idx(ptr %x, i32 zeroext %idx) nounwind {
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vadd.vv v8, v8, v8
-; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vslidedown.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32
+; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
@@ -310,7 +302,6 @@ define i64 @extractelt_v2i64_idx(ptr %x, i32 zeroext %idx) nounwind {
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vadd.vv v8, v8, v8
-; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vslidedown.vx v8, v8, a1
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
@@ -326,7 +317,6 @@ define half @extractelt_v8f16_idx(ptr %x, i32 zeroext %idx) nounwind {
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8
-; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@@ -342,7 +332,6 @@ define float @extractelt_v4f32_idx(ptr %x, i32 zeroext %idx) nounwind {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@@ -358,7 +347,6 @@ define double @extractelt_v2f64_idx(ptr %x, i32 zeroext %idx) nounwind {
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8
-; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@@ -529,8 +517,8 @@ define void @store_extractelt_v16i8(ptr %x, ptr %p) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
-; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 7
+; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
%a = load <16 x i8>, ptr %x
@@ -544,8 +532,8 @@ define void @store_extractelt_v8i16(ptr %x, ptr %p) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 7
+; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
%a = load <8 x i16>, ptr %x
@@ -559,8 +547,8 @@ define void @store_extractelt_v4i32(ptr %x, ptr %p) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vse32.v v8, (a1)
; CHECK-NEXT: ret
%a = load <4 x i32>, ptr %x
@@ -575,9 +563,9 @@ define void @store_extractelt_v2i64(ptr %x, ptr %p) nounwind {
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vle64.v v8, (a0)
-; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vslidedown.vi v8, v8, 1
; RV32-NEXT: li a0, 32
+; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: vmv.x.s a2, v8
@@ -589,8 +577,8 @@ define void @store_extractelt_v2i64(ptr %x, ptr %p) nounwind {
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a0)
-; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 1
+; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a1)
; RV64-NEXT: ret
%a = load <2 x i64>, ptr %x
@@ -604,8 +592,8 @@ define void @store_extractelt_v2f64(ptr %x, ptr %p) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
-; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 1
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret
%a = load <2 x double>, ptr %x
@@ -627,7 +615,6 @@ define i32 @extractelt_add_v4i32(<4 x i32> %x) {
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vadd.vi v8, v8, 13
-; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
@@ -650,7 +637,6 @@ define i32 @extractelt_sub_v4i32(<4 x i32> %x) {
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vrsub.vi v8, v8, 13
-; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
@@ -665,7 +651,6 @@ define i32 @extractelt_mul_v4i32(<4 x i32> %x) {
; RV32NOM-NEXT: li a0, 13
; RV32NOM-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32NOM-NEXT: vmul.vx v8, v8, a0
-; RV32NOM-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32NOM-NEXT: vslidedown.vi v8, v8, 2
; RV32NOM-NEXT: vmv.x.s a0, v8
; RV32NOM-NEXT: ret
@@ -684,7 +669,6 @@ define i32 @extractelt_mul_v4i32(<4 x i32> %x) {
; RV64-NEXT: li a0, 13
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vmul.vx v8, v8, a0
-; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
@@ -712,7 +696,6 @@ define i32 @extractelt_sdiv_v4i32(<4 x i32> %x) {
; RV32NOM-NEXT: vsra.vv v9, v8, v11
; RV32NOM-NEXT: vsrl.vi v8, v8, 31
; RV32NOM-NEXT: vadd.vv v8, v9, v8
-; RV32NOM-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32NOM-NEXT: vslidedown.vi v8, v8, 2
; RV32NOM-NEXT: vmv.x.s a0, v8
; RV32NOM-NEXT: ret
@@ -748,7 +731,6 @@ define i32 @extractelt_sdiv_v4i32(<4 x i32> %x) {
; RV64-NEXT: vsra.vv v8, v8, v11
; RV64-NEXT: vsrl.vi v9, v8, 31
; RV64-NEXT: vadd.vv v8, v8, v9
-; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
@@ -765,7 +747,6 @@ define i32 @extractelt_udiv_v4i32(<4 x i32> %x) {
; RV32NOM-NEXT: lui a0, 322639
; RV32NOM-NEXT: addi a0, a0, -945
; RV32NOM-NEXT: vmulhu.vx v8, v8, a0
-; RV32NOM-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32NOM-NEXT: vslidedown.vi v8, v8, 2
; RV32NOM-NEXT: vmv.x.s a0, v8
; RV32NOM-NEXT: srli a0, a0, 2
@@ -790,7 +771,6 @@ define i32 @extractelt_udiv_v4i32(<4 x i32> %x) {
; RV64-NEXT: addiw a0, a0, -945
; RV64-NEXT: vmulhu.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 2
-; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
index 135844362dba..8059f5b5c554 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
@@ -776,9 +776,9 @@ define void @copysign_neg_trunc_v3f16_v3f32(ptr %x, ptr %y) {
; LMULMAX1-RV32-NEXT: vle16.v v9, (a0)
; LMULMAX1-RV32-NEXT: vfncvt.f.f.w v10, v8
; LMULMAX1-RV32-NEXT: vfsgnjn.vv v8, v9, v10
-; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1-RV32-NEXT: addi a1, a0, 4
+; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX1-RV32-NEXT: vse16.v v9, (a1)
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
@@ -792,9 +792,9 @@ define void @copysign_neg_trunc_v3f16_v3f32(ptr %x, ptr %y) {
; LMULMAX1-RV64-NEXT: vle32.v v9, (a1)
; LMULMAX1-RV64-NEXT: vfncvt.f.f.w v10, v9
; LMULMAX1-RV64-NEXT: vfsgnjn.vv v8, v8, v10
-; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1-RV64-NEXT: addi a1, a0, 4
+; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX1-RV64-NEXT: vse16.v v9, (a1)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
index 608ea4b6f345..9b46d4441a21 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
@@ -191,7 +191,6 @@ define void @fp2si_v2f64_v2i8(ptr %x, ptr %y) {
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vle64.v v8, (a0)
-; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vslidedown.vi v9, v8, 1
; RV32-NEXT: vfmv.f.s fa5, v9
; RV32-NEXT: lui a0, %hi(.LCPI10_0)
@@ -211,7 +210,7 @@ define void @fp2si_v2f64_v2i8(ptr %x, ptr %y) {
; RV32-NEXT: fmin.d fa5, fa5, fa3
; RV32-NEXT: fcvt.w.d a3, fa5, rtz
; RV32-NEXT: and a2, a2, a3
-; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: vslide1down.vx v8, v8, a0
; RV32-NEXT: vse8.v v8, (a1)
@@ -221,7 +220,6 @@ define void @fp2si_v2f64_v2i8(ptr %x, ptr %y) {
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a0)
-; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vslidedown.vi v9, v8, 1
; RV64-NEXT: vfmv.f.s fa5, v9
; RV64-NEXT: lui a0, %hi(.LCPI10_0)
@@ -241,7 +239,7 @@ define void @fp2si_v2f64_v2i8(ptr %x, ptr %y) {
; RV64-NEXT: fmin.d fa5, fa5, fa3
; RV64-NEXT: fcvt.l.d a3, fa5, rtz
; RV64-NEXT: and a2, a2, a3
-; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: vslide1down.vx v8, v8, a0
; RV64-NEXT: vse8.v v8, (a1)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
index f453ba921f5c..88a5dbb1386a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
@@ -84,9 +84,9 @@ define void @fp2si_v3f32_v3i32(ptr %x, ptr %y) {
; LMULMAX8RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vle32.v v8, (a0)
; LMULMAX8RV32-NEXT: vfcvt.rtz.x.f.v v8, v8
-; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX8RV32-NEXT: addi a0, a1, 8
+; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vse32.v v9, (a0)
; LMULMAX8RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX8RV32-NEXT: vse32.v v8, (a1)
@@ -97,9 +97,9 @@ define void @fp2si_v3f32_v3i32(ptr %x, ptr %y) {
; LMULMAX8RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vle32.v v8, (a0)
; LMULMAX8RV64-NEXT: vfcvt.rtz.x.f.v v8, v8
-; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX8RV64-NEXT: addi a0, a1, 8
+; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vse32.v v9, (a0)
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX8RV64-NEXT: vse64.v v8, (a1)
@@ -110,9 +110,9 @@ define void @fp2si_v3f32_v3i32(ptr %x, ptr %y) {
; LMULMAX1RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1RV32-NEXT: vfcvt.rtz.x.f.v v8, v8
-; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1RV32-NEXT: addi a0, a1, 8
+; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vse32.v v9, (a0)
; LMULMAX1RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1RV32-NEXT: vse32.v v8, (a1)
@@ -123,9 +123,9 @@ define void @fp2si_v3f32_v3i32(ptr %x, ptr %y) {
; LMULMAX1RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1RV64-NEXT: vfcvt.rtz.x.f.v v8, v8
-; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1RV64-NEXT: addi a0, a1, 8
+; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vse32.v v9, (a0)
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1RV64-NEXT: vse64.v v8, (a1)
@@ -142,9 +142,9 @@ define void @fp2ui_v3f32_v3i32(ptr %x, ptr %y) {
; LMULMAX8RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vle32.v v8, (a0)
; LMULMAX8RV32-NEXT: vfcvt.rtz.xu.f.v v8, v8
-; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX8RV32-NEXT: addi a0, a1, 8
+; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vse32.v v9, (a0)
; LMULMAX8RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX8RV32-NEXT: vse32.v v8, (a1)
@@ -155,9 +155,9 @@ define void @fp2ui_v3f32_v3i32(ptr %x, ptr %y) {
; LMULMAX8RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vle32.v v8, (a0)
; LMULMAX8RV64-NEXT: vfcvt.rtz.xu.f.v v8, v8
-; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX8RV64-NEXT: addi a0, a1, 8
+; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vse32.v v9, (a0)
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX8RV64-NEXT: vse64.v v8, (a1)
@@ -168,9 +168,9 @@ define void @fp2ui_v3f32_v3i32(ptr %x, ptr %y) {
; LMULMAX1RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1RV32-NEXT: vfcvt.rtz.xu.f.v v8, v8
-; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1RV32-NEXT: addi a0, a1, 8
+; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vse32.v v9, (a0)
; LMULMAX1RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1RV32-NEXT: vse32.v v8, (a1)
@@ -181,9 +181,9 @@ define void @fp2ui_v3f32_v3i32(ptr %x, ptr %y) {
; LMULMAX1RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1RV64-NEXT: vfcvt.rtz.xu.f.v v8, v8
-; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1RV64-NEXT: addi a0, a1, 8
+; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vse32.v v9, (a0)
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1RV64-NEXT: vse64.v v8, (a1)
@@ -212,7 +212,6 @@ define <3 x i15> @fp2si_v3f32_v3i15(<3 x float> %x) {
; LMULMAX8RV32: # %bb.0:
; LMULMAX8RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; LMULMAX8RV32-NEXT: vfncvt.rtz.x.f.w v9, v8
-; LMULMAX8RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX8RV32-NEXT: vslidedown.vi v8, v9, 2
; LMULMAX8RV32-NEXT: vmv.x.s a1, v8
; LMULMAX8RV32-NEXT: slli a2, a1, 17
@@ -240,7 +239,6 @@ define <3 x i15> @fp2si_v3f32_v3i15(<3 x float> %x) {
; LMULMAX8RV64-NEXT: lui a2, 8
; LMULMAX8RV64-NEXT: addiw a2, a2, -1
; LMULMAX8RV64-NEXT: and a1, a1, a2
-; LMULMAX8RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX8RV64-NEXT: vslidedown.vi v8, v9, 1
; LMULMAX8RV64-NEXT: vmv.x.s a3, v8
; LMULMAX8RV64-NEXT: and a2, a3, a2
@@ -260,7 +258,6 @@ define <3 x i15> @fp2si_v3f32_v3i15(<3 x float> %x) {
; LMULMAX1RV32: # %bb.0:
; LMULMAX1RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; LMULMAX1RV32-NEXT: vfncvt.rtz.x.f.w v9, v8
-; LMULMAX1RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX1RV32-NEXT: vslidedown.vi v8, v9, 2
; LMULMAX1RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1RV32-NEXT: slli a2, a1, 17
@@ -288,7 +285,6 @@ define <3 x i15> @fp2si_v3f32_v3i15(<3 x float> %x) {
; LMULMAX1RV64-NEXT: lui a2, 8
; LMULMAX1RV64-NEXT: addiw a2, a2, -1
; LMULMAX1RV64-NEXT: and a1, a1, a2
-; LMULMAX1RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX1RV64-NEXT: vslidedown.vi v8, v9, 1
; LMULMAX1RV64-NEXT: vmv.x.s a3, v8
; LMULMAX1RV64-NEXT: and a2, a3, a2
@@ -313,7 +309,6 @@ define <3 x i15> @fp2ui_v3f32_v3i15(<3 x float> %x) {
; LMULMAX8RV32: # %bb.0:
; LMULMAX8RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; LMULMAX8RV32-NEXT: vfncvt.rtz.x.f.w v9, v8
-; LMULMAX8RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX8RV32-NEXT: vslidedown.vi v8, v9, 2
; LMULMAX8RV32-NEXT: vmv.x.s a1, v8
; LMULMAX8RV32-NEXT: slli a2, a1, 17
@@ -341,7 +336,6 @@ define <3 x i15> @fp2ui_v3f32_v3i15(<3 x float> %x) {
; LMULMAX8RV64-NEXT: lui a2, 16
; LMULMAX8RV64-NEXT: addiw a2, a2, -1
; LMULMAX8RV64-NEXT: and a1, a1, a2
-; LMULMAX8RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX8RV64-NEXT: vslidedown.vi v8, v9, 1
; LMULMAX8RV64-NEXT: vmv.x.s a3, v8
; LMULMAX8RV64-NEXT: and a2, a3, a2
@@ -361,7 +355,6 @@ define <3 x i15> @fp2ui_v3f32_v3i15(<3 x float> %x) {
; LMULMAX1RV32: # %bb.0:
; LMULMAX1RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; LMULMAX1RV32-NEXT: vfncvt.rtz.x.f.w v9, v8
-; LMULMAX1RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX1RV32-NEXT: vslidedown.vi v8, v9, 2
; LMULMAX1RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1RV32-NEXT: slli a2, a1, 17
@@ -389,7 +382,6 @@ define <3 x i15> @fp2ui_v3f32_v3i15(<3 x float> %x) {
; LMULMAX1RV64-NEXT: lui a2, 16
; LMULMAX1RV64-NEXT: addiw a2, a2, -1
; LMULMAX1RV64-NEXT: and a1, a1, a2
-; LMULMAX1RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX1RV64-NEXT: vslidedown.vi v8, v9, 1
; LMULMAX1RV64-NEXT: vmv.x.s a3, v8
; LMULMAX1RV64-NEXT: and a2, a3, a2
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
index 65603e634c72..b60f9405a760 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
@@ -90,9 +90,9 @@ define void @si2fp_v3i32_v3f32(ptr %x, ptr %y) {
; LMULMAX8RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vle32.v v8, (a0)
; LMULMAX8RV32-NEXT: vfcvt.f.x.v v8, v8
-; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX8RV32-NEXT: addi a0, a1, 8
+; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vse32.v v9, (a0)
; LMULMAX8RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX8RV32-NEXT: vse32.v v8, (a1)
@@ -103,9 +103,9 @@ define void @si2fp_v3i32_v3f32(ptr %x, ptr %y) {
; LMULMAX8RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vle32.v v8, (a0)
; LMULMAX8RV64-NEXT: vfcvt.f.x.v v8, v8
-; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX8RV64-NEXT: addi a0, a1, 8
+; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vse32.v v9, (a0)
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX8RV64-NEXT: vse64.v v8, (a1)
@@ -116,9 +116,9 @@ define void @si2fp_v3i32_v3f32(ptr %x, ptr %y) {
; LMULMAX1RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1RV32-NEXT: vfcvt.f.x.v v8, v8
-; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1RV32-NEXT: addi a0, a1, 8
+; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vse32.v v9, (a0)
; LMULMAX1RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1RV32-NEXT: vse32.v v8, (a1)
@@ -129,9 +129,9 @@ define void @si2fp_v3i32_v3f32(ptr %x, ptr %y) {
; LMULMAX1RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1RV64-NEXT: vfcvt.f.x.v v8, v8
-; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1RV64-NEXT: addi a0, a1, 8
+; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vse32.v v9, (a0)
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1RV64-NEXT: vse64.v v8, (a1)
@@ -148,9 +148,9 @@ define void @ui2fp_v3i32_v3f32(ptr %x, ptr %y) {
; LMULMAX8RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vle32.v v8, (a0)
; LMULMAX8RV32-NEXT: vfcvt.f.xu.v v8, v8
-; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX8RV32-NEXT: addi a0, a1, 8
+; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vse32.v v9, (a0)
; LMULMAX8RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX8RV32-NEXT: vse32.v v8, (a1)
@@ -161,9 +161,9 @@ define void @ui2fp_v3i32_v3f32(ptr %x, ptr %y) {
; LMULMAX8RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vle32.v v8, (a0)
; LMULMAX8RV64-NEXT: vfcvt.f.xu.v v8, v8
-; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX8RV64-NEXT: addi a0, a1, 8
+; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vse32.v v9, (a0)
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX8RV64-NEXT: vse64.v v8, (a1)
@@ -174,9 +174,9 @@ define void @ui2fp_v3i32_v3f32(ptr %x, ptr %y) {
; LMULMAX1RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1RV32-NEXT: vfcvt.f.xu.v v8, v8
-; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1RV32-NEXT: addi a0, a1, 8
+; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vse32.v v9, (a0)
; LMULMAX1RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1RV32-NEXT: vse32.v v8, (a1)
@@ -187,9 +187,9 @@ define void @ui2fp_v3i32_v3f32(ptr %x, ptr %y) {
; LMULMAX1RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1RV64-NEXT: vfcvt.f.xu.v v8, v8
-; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1RV64-NEXT: addi a0, a1, 8
+; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vse32.v v9, (a0)
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1RV64-NEXT: vse64.v v8, (a1)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
index 48a7f8bf6de8..3aeb31770c75 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
@@ -330,7 +330,6 @@ define <2 x i64> @mgather_v2i8_sextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2 x
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV32ZVE32F-NEXT: vslidedown.vi v8, v9, 1
; RV32ZVE32F-NEXT: vmv.x.s a1, v8
; RV32ZVE32F-NEXT: srai a2, a1, 31
@@ -392,7 +391,6 @@ define <2 x i64> @mgather_v2i8_zextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2 x
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV32ZVE32F-NEXT: vslidedown.vi v8, v9, 1
; RV32ZVE32F-NEXT: vmv.x.s a1, v8
; RV32ZVE32F-NEXT: andi a1, a1, 255
@@ -1061,7 +1059,6 @@ define <2 x i64> @mgather_v2i16_sextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV32ZVE32F-NEXT: vslidedown.vi v8, v9, 1
; RV32ZVE32F-NEXT: vmv.x.s a1, v8
; RV32ZVE32F-NEXT: srai a2, a1, 31
@@ -1123,7 +1120,6 @@ define <2 x i64> @mgather_v2i16_zextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, mu
; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV32ZVE32F-NEXT: vslidedown.vi v8, v9, 1
; RV32ZVE32F-NEXT: vmv.x.s a1, v8
; RV32ZVE32F-NEXT: lui a2, 16
@@ -2158,12 +2154,12 @@ define <2 x i64> @mgather_v2i32_sextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32ZVE32F-NEXT: vslidedown.vi v8, v9, 1
; RV32ZVE32F-NEXT: vmv.x.s a1, v8
; RV32ZVE32F-NEXT: srai a1, a1, 31
; RV32ZVE32F-NEXT: vmv.x.s a2, v9
; RV32ZVE32F-NEXT: srai a2, a2, 31
+; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32ZVE32F-NEXT: vse32.v v9, (a0)
; RV32ZVE32F-NEXT: addi a3, a0, 8
; RV32ZVE32F-NEXT: vse32.v v8, (a3)
@@ -2221,10 +2217,10 @@ define <2 x i64> @mgather_v2i32_zextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2
; RV32ZVE32F: # %bb.0:
; RV32ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t
-; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32ZVE32F-NEXT: vslidedown.vi v8, v9, 1
; RV32ZVE32F-NEXT: sw zero, 12(a0)
; RV32ZVE32F-NEXT: sw zero, 4(a0)
+; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32ZVE32F-NEXT: vse32.v v9, (a0)
; RV32ZVE32F-NEXT: addi a0, a0, 8
; RV32ZVE32F-NEXT: vse32.v v8, (a0)
@@ -4523,7 +4519,6 @@ define <8 x i64> @mgather_baseidx_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8 x i1>
; RV64ZVE32F-NEXT: andi a6, a6, -128
; RV64ZVE32F-NEXT: beqz a6, .LBB48_17
; RV64ZVE32F-NEXT: .LBB48_19: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
@@ -4802,7 +4797,6 @@ define <8 x i64> @mgather_baseidx_sext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: andi a6, a6, -128
; RV64ZVE32F-NEXT: beqz a6, .LBB49_17
; RV64ZVE32F-NEXT: .LBB49_19: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
@@ -5089,7 +5083,6 @@ define <8 x i64> @mgather_baseidx_zext_v8i8_v8i64(ptr %base, <8 x i8> %idxs, <8
; RV64ZVE32F-NEXT: andi a5, a5, -128
; RV64ZVE32F-NEXT: beqz a5, .LBB50_17
; RV64ZVE32F-NEXT: .LBB50_19: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: andi a2, a2, 255
@@ -5273,8 +5266,8 @@ define <8 x i64> @mgather_baseidx_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-LABEL: mgather_baseidx_v8i16_v8i64:
; RV64ZVE32F: # %bb.0:
; RV64ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a6, v0
-; RV64ZVE32F-NEXT: andi a3, a6, 1
+; RV64ZVE32F-NEXT: vmv.x.s a5, v0
+; RV64ZVE32F-NEXT: andi a3, a5, 1
; RV64ZVE32F-NEXT: beqz a3, .LBB51_3
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
@@ -5282,14 +5275,14 @@ define <8 x i64> @mgather_baseidx_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: ld a3, 0(a3)
-; RV64ZVE32F-NEXT: andi a4, a6, 2
+; RV64ZVE32F-NEXT: andi a4, a5, 2
; RV64ZVE32F-NEXT: bnez a4, .LBB51_4
; RV64ZVE32F-NEXT: .LBB51_2:
; RV64ZVE32F-NEXT: ld a4, 8(a2)
; RV64ZVE32F-NEXT: j .LBB51_5
; RV64ZVE32F-NEXT: .LBB51_3:
; RV64ZVE32F-NEXT: ld a3, 0(a2)
-; RV64ZVE32F-NEXT: andi a4, a6, 2
+; RV64ZVE32F-NEXT: andi a4, a5, 2
; RV64ZVE32F-NEXT: beqz a4, .LBB51_2
; RV64ZVE32F-NEXT: .LBB51_4: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
@@ -5300,20 +5293,20 @@ define <8 x i64> @mgather_baseidx_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: ld a4, 0(a4)
; RV64ZVE32F-NEXT: .LBB51_5: # %else2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: andi a5, a6, 4
+; RV64ZVE32F-NEXT: andi a6, a5, 4
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: beqz a5, .LBB51_7
+; RV64ZVE32F-NEXT: beqz a6, .LBB51_7
; RV64ZVE32F-NEXT: # %bb.6: # %cond.load4
-; RV64ZVE32F-NEXT: vmv.x.s a5, v9
-; RV64ZVE32F-NEXT: slli a5, a5, 3
-; RV64ZVE32F-NEXT: add a5, a1, a5
-; RV64ZVE32F-NEXT: ld a5, 0(a5)
+; RV64ZVE32F-NEXT: vmv.x.s a6, v9
+; RV64ZVE32F-NEXT: slli a6, a6, 3
+; RV64ZVE32F-NEXT: add a6, a1, a6
+; RV64ZVE32F-NEXT: ld a6, 0(a6)
; RV64ZVE32F-NEXT: j .LBB51_8
; RV64ZVE32F-NEXT: .LBB51_7:
-; RV64ZVE32F-NEXT: ld a5, 16(a2)
+; RV64ZVE32F-NEXT: ld a6, 16(a2)
; RV64ZVE32F-NEXT: .LBB51_8: # %else5
; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: andi a7, a6, 8
+; RV64ZVE32F-NEXT: andi a7, a5, 8
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
; RV64ZVE32F-NEXT: beqz a7, .LBB51_12
; RV64ZVE32F-NEXT: # %bb.9: # %cond.load7
@@ -5323,18 +5316,18 @@ define <8 x i64> @mgather_baseidx_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli a7, a7, 3
; RV64ZVE32F-NEXT: add a7, a1, a7
; RV64ZVE32F-NEXT: ld a7, 0(a7)
-; RV64ZVE32F-NEXT: andi t0, a6, 16
+; RV64ZVE32F-NEXT: andi t0, a5, 16
; RV64ZVE32F-NEXT: bnez t0, .LBB51_13
; RV64ZVE32F-NEXT: .LBB51_10:
; RV64ZVE32F-NEXT: ld t0, 32(a2)
-; RV64ZVE32F-NEXT: andi t1, a6, 32
+; RV64ZVE32F-NEXT: andi t1, a5, 32
; RV64ZVE32F-NEXT: bnez t1, .LBB51_14
; RV64ZVE32F-NEXT: .LBB51_11:
; RV64ZVE32F-NEXT: ld t1, 40(a2)
; RV64ZVE32F-NEXT: j .LBB51_15
; RV64ZVE32F-NEXT: .LBB51_12:
; RV64ZVE32F-NEXT: ld a7, 24(a2)
-; RV64ZVE32F-NEXT: andi t0, a6, 16
+; RV64ZVE32F-NEXT: andi t0, a5, 16
; RV64ZVE32F-NEXT: beqz t0, .LBB51_10
; RV64ZVE32F-NEXT: .LBB51_13: # %cond.load10
; RV64ZVE32F-NEXT: vsetivli zero, 0, e16, mf2, ta, ma
@@ -5342,7 +5335,7 @@ define <8 x i64> @mgather_baseidx_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli t0, t0, 3
; RV64ZVE32F-NEXT: add t0, a1, t0
; RV64ZVE32F-NEXT: ld t0, 0(t0)
-; RV64ZVE32F-NEXT: andi t1, a6, 32
+; RV64ZVE32F-NEXT: andi t1, a5, 32
; RV64ZVE32F-NEXT: beqz t1, .LBB51_11
; RV64ZVE32F-NEXT: .LBB51_14: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
@@ -5353,7 +5346,7 @@ define <8 x i64> @mgather_baseidx_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: ld t1, 0(t1)
; RV64ZVE32F-NEXT: .LBB51_15: # %else14
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: andi t2, a6, 64
+; RV64ZVE32F-NEXT: andi t2, a5, 64
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: beqz t2, .LBB51_18
; RV64ZVE32F-NEXT: # %bb.16: # %cond.load16
@@ -5361,17 +5354,16 @@ define <8 x i64> @mgather_baseidx_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: slli t2, t2, 3
; RV64ZVE32F-NEXT: add t2, a1, t2
; RV64ZVE32F-NEXT: ld t2, 0(t2)
-; RV64ZVE32F-NEXT: andi a6, a6, -128
-; RV64ZVE32F-NEXT: bnez a6, .LBB51_19
+; RV64ZVE32F-NEXT: andi a5, a5, -128
+; RV64ZVE32F-NEXT: bnez a5, .LBB51_19
; RV64ZVE32F-NEXT: .LBB51_17:
; RV64ZVE32F-NEXT: ld a1, 56(a2)
; RV64ZVE32F-NEXT: j .LBB51_20
; RV64ZVE32F-NEXT: .LBB51_18:
; RV64ZVE32F-NEXT: ld t2, 48(a2)
-; RV64ZVE32F-NEXT: andi a6, a6, -128
-; RV64ZVE32F-NEXT: beqz a6, .LBB51_17
+; RV64ZVE32F-NEXT: andi a5, a5, -128
+; RV64ZVE32F-NEXT: beqz a5, .LBB51_17
; RV64ZVE32F-NEXT: .LBB51_19: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
@@ -5380,7 +5372,7 @@ define <8 x i64> @mgather_baseidx_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <8 x i
; RV64ZVE32F-NEXT: .LBB51_20: # %else20
; RV64ZVE32F-NEXT: sd a3, 0(a0)
; RV64ZVE32F-NEXT: sd a4, 8(a0)
-; RV64ZVE32F-NEXT: sd a5, 16(a0)
+; RV64ZVE32F-NEXT: sd a6, 16(a0)
; RV64ZVE32F-NEXT: sd a7, 24(a0)
; RV64ZVE32F-NEXT: sd t0, 32(a0)
; RV64ZVE32F-NEXT: sd t1, 40(a0)
@@ -5553,8 +5545,8 @@ define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-LABEL: mgather_baseidx_sext_v8i16_v8i64:
; RV64ZVE32F: # %bb.0:
; RV64ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, ma
-; RV64ZVE32F-NEXT: vmv.x.s a6, v0
-; RV64ZVE32F-NEXT: andi a3, a6, 1
+; RV64ZVE32F-NEXT: vmv.x.s a5, v0
+; RV64ZVE32F-NEXT: andi a3, a5, 1
; RV64ZVE32F-NEXT: beqz a3, .LBB52_3
; RV64ZVE32F-NEXT: # %bb.1: # %cond.load
; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
@@ -5562,14 +5554,14 @@ define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: ld a3, 0(a3)
-; RV64ZVE32F-NEXT: andi a4, a6, 2
+; RV64ZVE32F-NEXT: andi a4, a5, 2
; RV64ZVE32F-NEXT: bnez a4, .LBB52_4
; RV64ZVE32F-NEXT: .LBB52_2:
; RV64ZVE32F-NEXT: ld a4, 8(a2)
; RV64ZVE32F-NEXT: j .LBB52_5
; RV64ZVE32F-NEXT: .LBB52_3:
; RV64ZVE32F-NEXT: ld a3, 0(a2)
-; RV64ZVE32F-NEXT: andi a4, a6, 2
+; RV64ZVE32F-NEXT: andi a4, a5, 2
; RV64ZVE32F-NEXT: beqz a4, .LBB52_2
; RV64ZVE32F-NEXT: .LBB52_4: # %cond.load1
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
@@ -5580,20 +5572,20 @@ define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: ld a4, 0(a4)
; RV64ZVE32F-NEXT: .LBB52_5: # %else2
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: andi a5, a6, 4
+; RV64ZVE32F-NEXT: andi a6, a5, 4
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2
-; RV64ZVE32F-NEXT: beqz a5, .LBB52_7
+; RV64ZVE32F-NEXT: beqz a6, .LBB52_7
; RV64ZVE32F-NEXT: # %bb.6: # %cond.load4
-; RV64ZVE32F-NEXT: vmv.x.s a5, v9
-; RV64ZVE32F-NEXT: slli a5, a5, 3
-; RV64ZVE32F-NEXT: add a5, a1, a5
-; RV64ZVE32F-NEXT: ld a5, 0(a5)
+; RV64ZVE32F-NEXT: vmv.x.s a6, v9
+; RV64ZVE32F-NEXT: slli a6, a6, 3
+; RV64ZVE32F-NEXT: add a6, a1, a6
+; RV64ZVE32F-NEXT: ld a6, 0(a6)
; RV64ZVE32F-NEXT: j .LBB52_8
; RV64ZVE32F-NEXT: .LBB52_7:
-; RV64ZVE32F-NEXT: ld a5, 16(a2)
+; RV64ZVE32F-NEXT: ld a6, 16(a2)
; RV64ZVE32F-NEXT: .LBB52_8: # %else5
; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma
-; RV64ZVE32F-NEXT: andi a7, a6, 8
+; RV64ZVE32F-NEXT: andi a7, a5, 8
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4
; RV64ZVE32F-NEXT: beqz a7, .LBB52_12
; RV64ZVE32F-NEXT: # %bb.9: # %cond.load7
@@ -5603,18 +5595,18 @@ define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: slli a7, a7, 3
; RV64ZVE32F-NEXT: add a7, a1, a7
; RV64ZVE32F-NEXT: ld a7, 0(a7)
-; RV64ZVE32F-NEXT: andi t0, a6, 16
+; RV64ZVE32F-NEXT: andi t0, a5, 16
; RV64ZVE32F-NEXT: bnez t0, .LBB52_13
; RV64ZVE32F-NEXT: .LBB52_10:
; RV64ZVE32F-NEXT: ld t0, 32(a2)
-; RV64ZVE32F-NEXT: andi t1, a6, 32
+; RV64ZVE32F-NEXT: andi t1, a5, 32
; RV64ZVE32F-NEXT: bnez t1, .LBB52_14
; RV64ZVE32F-NEXT: .LBB52_11:
; RV64ZVE32F-NEXT: ld t1, 40(a2)
; RV64ZVE32F-NEXT: j .LBB52_15
; RV64ZVE32F-NEXT: .LBB52_12:
; RV64ZVE32F-NEXT: ld a7, 24(a2)
-; RV64ZVE32F-NEXT: andi t0, a6, 16
+; RV64ZVE32F-NEXT: andi t0, a5, 16
; RV64ZVE32F-NEXT: beqz t0, .LBB52_10
; RV64ZVE32F-NEXT: .LBB52_13: # %cond.load10
; RV64ZVE32F-NEXT: vsetivli zero, 0, e16, mf2, ta, ma
@@ -5622,7 +5614,7 @@ define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: slli t0, t0, 3
; RV64ZVE32F-NEXT: add t0, a1, t0
; RV64ZVE32F-NEXT: ld t0, 0(t0)
-; RV64ZVE32F-NEXT: andi t1, a6, 32
+; RV64ZVE32F-NEXT: andi t1, a5, 32
; RV64ZVE32F-NEXT: beqz t1, .LBB52_11
; RV64ZVE32F-NEXT: .LBB52_14: # %cond.load13
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
@@ -5633,7 +5625,7 @@ define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: ld t1, 0(t1)
; RV64ZVE32F-NEXT: .LBB52_15: # %else14
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
-; RV64ZVE32F-NEXT: andi t2, a6, 64
+; RV64ZVE32F-NEXT: andi t2, a5, 64
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2
; RV64ZVE32F-NEXT: beqz t2, .LBB52_18
; RV64ZVE32F-NEXT: # %bb.16: # %cond.load16
@@ -5641,17 +5633,16 @@ define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: slli t2, t2, 3
; RV64ZVE32F-NEXT: add t2, a1, t2
; RV64ZVE32F-NEXT: ld t2, 0(t2)
-; RV64ZVE32F-NEXT: andi a6, a6, -128
-; RV64ZVE32F-NEXT: bnez a6, .LBB52_19
+; RV64ZVE32F-NEXT: andi a5, a5, -128
+; RV64ZVE32F-NEXT: bnez a5, .LBB52_19
; RV64ZVE32F-NEXT: .LBB52_17:
; RV64ZVE32F-NEXT: ld a1, 56(a2)
; RV64ZVE32F-NEXT: j .LBB52_20
; RV64ZVE32F-NEXT: .LBB52_18:
; RV64ZVE32F-NEXT: ld t2, 48(a2)
-; RV64ZVE32F-NEXT: andi a6, a6, -128
-; RV64ZVE32F-NEXT: beqz a6, .LBB52_17
+; RV64ZVE32F-NEXT: andi a5, a5, -128
+; RV64ZVE32F-NEXT: beqz a5, .LBB52_17
; RV64ZVE32F-NEXT: .LBB52_19: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
@@ -5660,7 +5651,7 @@ define <8 x i64> @mgather_baseidx_sext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: .LBB52_20: # %else20
; RV64ZVE32F-NEXT: sd a3, 0(a0)
; RV64ZVE32F-NEXT: sd a4, 8(a0)
-; RV64ZVE32F-NEXT: sd a5, 16(a0)
+; RV64ZVE32F-NEXT: sd a6, 16(a0)
; RV64ZVE32F-NEXT: sd a7, 24(a0)
; RV64ZVE32F-NEXT: sd t0, 32(a0)
; RV64ZVE32F-NEXT: sd t1, 40(a0)
@@ -5941,7 +5932,6 @@ define <8 x i64> @mgather_baseidx_zext_v8i16_v8i64(ptr %base, <8 x i16> %idxs, <
; RV64ZVE32F-NEXT: andi a6, a6, -128
; RV64ZVE32F-NEXT: beqz a6, .LBB53_17
; RV64ZVE32F-NEXT: .LBB53_19: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: and a2, a2, a5
@@ -6178,7 +6168,6 @@ define <8 x i64> @mgather_baseidx_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <8 x i
; RV64ZVE32F-NEXT: andi a7, a5, 8
; RV64ZVE32F-NEXT: beqz a7, .LBB54_7
; RV64ZVE32F-NEXT: .LBB54_11: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a7, v8
; RV64ZVE32F-NEXT: slli a7, a7, 3
@@ -6187,7 +6176,6 @@ define <8 x i64> @mgather_baseidx_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <8 x i
; RV64ZVE32F-NEXT: andi t0, a5, 16
; RV64ZVE32F-NEXT: beqz t0, .LBB54_8
; RV64ZVE32F-NEXT: .LBB54_12: # %cond.load10
-; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s t0, v10
; RV64ZVE32F-NEXT: slli t0, t0, 3
; RV64ZVE32F-NEXT: add t0, a1, t0
@@ -6195,14 +6183,12 @@ define <8 x i64> @mgather_baseidx_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <8 x i
; RV64ZVE32F-NEXT: andi t1, a5, 32
; RV64ZVE32F-NEXT: beqz t1, .LBB54_9
; RV64ZVE32F-NEXT: .LBB54_13: # %cond.load13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s t1, v8
; RV64ZVE32F-NEXT: slli t1, t1, 3
; RV64ZVE32F-NEXT: add t1, a1, t1
; RV64ZVE32F-NEXT: ld t1, 0(t1)
; RV64ZVE32F-NEXT: .LBB54_14: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: andi t2, a5, 64
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2
; RV64ZVE32F-NEXT: beqz t2, .LBB54_17
@@ -6221,7 +6207,6 @@ define <8 x i64> @mgather_baseidx_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <8 x i
; RV64ZVE32F-NEXT: andi a5, a5, -128
; RV64ZVE32F-NEXT: beqz a5, .LBB54_16
; RV64ZVE32F-NEXT: .LBB54_18: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
@@ -6456,7 +6441,6 @@ define <8 x i64> @mgather_baseidx_sext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: andi a7, a5, 8
; RV64ZVE32F-NEXT: beqz a7, .LBB55_7
; RV64ZVE32F-NEXT: .LBB55_11: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a7, v8
; RV64ZVE32F-NEXT: slli a7, a7, 3
@@ -6465,7 +6449,6 @@ define <8 x i64> @mgather_baseidx_sext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: andi t0, a5, 16
; RV64ZVE32F-NEXT: beqz t0, .LBB55_8
; RV64ZVE32F-NEXT: .LBB55_12: # %cond.load10
-; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s t0, v10
; RV64ZVE32F-NEXT: slli t0, t0, 3
; RV64ZVE32F-NEXT: add t0, a1, t0
@@ -6473,14 +6456,12 @@ define <8 x i64> @mgather_baseidx_sext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: andi t1, a5, 32
; RV64ZVE32F-NEXT: beqz t1, .LBB55_9
; RV64ZVE32F-NEXT: .LBB55_13: # %cond.load13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s t1, v8
; RV64ZVE32F-NEXT: slli t1, t1, 3
; RV64ZVE32F-NEXT: add t1, a1, t1
; RV64ZVE32F-NEXT: ld t1, 0(t1)
; RV64ZVE32F-NEXT: .LBB55_14: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: andi t2, a5, 64
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2
; RV64ZVE32F-NEXT: beqz t2, .LBB55_17
@@ -6499,7 +6480,6 @@ define <8 x i64> @mgather_baseidx_sext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: andi a5, a5, -128
; RV64ZVE32F-NEXT: beqz a5, .LBB55_16
; RV64ZVE32F-NEXT: .LBB55_18: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
@@ -6738,7 +6718,6 @@ define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: andi a7, a5, 8
; RV64ZVE32F-NEXT: beqz a7, .LBB56_7
; RV64ZVE32F-NEXT: .LBB56_11: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a7, v8
; RV64ZVE32F-NEXT: slli a7, a7, 32
@@ -6748,7 +6727,6 @@ define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: andi t0, a5, 16
; RV64ZVE32F-NEXT: beqz t0, .LBB56_8
; RV64ZVE32F-NEXT: .LBB56_12: # %cond.load10
-; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s t0, v10
; RV64ZVE32F-NEXT: slli t0, t0, 32
; RV64ZVE32F-NEXT: srli t0, t0, 29
@@ -6757,7 +6735,6 @@ define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: andi t1, a5, 32
; RV64ZVE32F-NEXT: beqz t1, .LBB56_9
; RV64ZVE32F-NEXT: .LBB56_13: # %cond.load13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s t1, v8
; RV64ZVE32F-NEXT: slli t1, t1, 32
@@ -6765,7 +6742,6 @@ define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: add t1, a1, t1
; RV64ZVE32F-NEXT: ld t1, 0(t1)
; RV64ZVE32F-NEXT: .LBB56_14: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: andi t2, a5, 64
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2
; RV64ZVE32F-NEXT: beqz t2, .LBB56_17
@@ -6785,7 +6761,6 @@ define <8 x i64> @mgather_baseidx_zext_v8i32_v8i64(ptr %base, <8 x i32> %idxs, <
; RV64ZVE32F-NEXT: andi a5, a5, -128
; RV64ZVE32F-NEXT: beqz a5, .LBB56_16
; RV64ZVE32F-NEXT: .LBB56_18: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 32
@@ -10200,7 +10175,6 @@ define <8 x double> @mgather_baseidx_v8i8_v8f64(ptr %base, <8 x i8> %idxs, <8 x
; RV64ZVE32F-NEXT: andi a2, a2, -128
; RV64ZVE32F-NEXT: beqz a2, .LBB87_14
; RV64ZVE32F-NEXT: # %bb.13: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
@@ -10418,7 +10392,6 @@ define <8 x double> @mgather_baseidx_sext_v8i8_v8f64(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: andi a2, a2, -128
; RV64ZVE32F-NEXT: beqz a2, .LBB88_14
; RV64ZVE32F-NEXT: # %bb.13: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
@@ -10642,7 +10615,6 @@ define <8 x double> @mgather_baseidx_zext_v8i8_v8f64(ptr %base, <8 x i8> %idxs,
; RV64ZVE32F-NEXT: andi a2, a2, -128
; RV64ZVE32F-NEXT: beqz a2, .LBB89_14
; RV64ZVE32F-NEXT: # %bb.13: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: andi a2, a2, 255
@@ -10865,7 +10837,6 @@ define <8 x double> @mgather_baseidx_v8i16_v8f64(ptr %base, <8 x i16> %idxs, <8
; RV64ZVE32F-NEXT: andi a2, a2, -128
; RV64ZVE32F-NEXT: beqz a2, .LBB90_14
; RV64ZVE32F-NEXT: # %bb.13: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
@@ -11084,7 +11055,6 @@ define <8 x double> @mgather_baseidx_sext_v8i16_v8f64(ptr %base, <8 x i16> %idxs
; RV64ZVE32F-NEXT: andi a2, a2, -128
; RV64ZVE32F-NEXT: beqz a2, .LBB91_14
; RV64ZVE32F-NEXT: # %bb.13: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
@@ -11311,7 +11281,6 @@ define <8 x double> @mgather_baseidx_zext_v8i16_v8f64(ptr %base, <8 x i16> %idxs
; RV64ZVE32F-NEXT: andi a3, a3, -128
; RV64ZVE32F-NEXT: beqz a3, .LBB92_14
; RV64ZVE32F-NEXT: # %bb.13: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: and a2, a3, a2
@@ -11507,14 +11476,12 @@ define <8 x double> @mgather_baseidx_v8i32_v8f64(ptr %base, <8 x i32> %idxs, <8
; RV64ZVE32F-NEXT: andi a3, a2, 32
; RV64ZVE32F-NEXT: beqz a3, .LBB93_9
; RV64ZVE32F-NEXT: .LBB93_8: # %cond.load13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa5, 0(a3)
; RV64ZVE32F-NEXT: .LBB93_9: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: andi a3, a2, 64
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2
; RV64ZVE32F-NEXT: beqz a3, .LBB93_11
@@ -11527,7 +11494,6 @@ define <8 x double> @mgather_baseidx_v8i32_v8f64(ptr %base, <8 x i32> %idxs, <8
; RV64ZVE32F-NEXT: andi a2, a2, -128
; RV64ZVE32F-NEXT: beqz a2, .LBB93_13
; RV64ZVE32F-NEXT: # %bb.12: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
@@ -11551,7 +11517,6 @@ define <8 x double> @mgather_baseidx_v8i32_v8f64(ptr %base, <8 x i32> %idxs, <8
; RV64ZVE32F-NEXT: andi a3, a2, 8
; RV64ZVE32F-NEXT: beqz a3, .LBB93_6
; RV64ZVE32F-NEXT: .LBB93_15: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 3
@@ -11560,7 +11525,6 @@ define <8 x double> @mgather_baseidx_v8i32_v8f64(ptr %base, <8 x i32> %idxs, <8
; RV64ZVE32F-NEXT: andi a3, a2, 16
; RV64ZVE32F-NEXT: beqz a3, .LBB93_7
; RV64ZVE32F-NEXT: .LBB93_16: # %cond.load10
-; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
@@ -11726,14 +11690,12 @@ define <8 x double> @mgather_baseidx_sext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
; RV64ZVE32F-NEXT: andi a3, a2, 32
; RV64ZVE32F-NEXT: beqz a3, .LBB94_9
; RV64ZVE32F-NEXT: .LBB94_8: # %cond.load13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa5, 0(a3)
; RV64ZVE32F-NEXT: .LBB94_9: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: andi a3, a2, 64
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2
; RV64ZVE32F-NEXT: beqz a3, .LBB94_11
@@ -11746,7 +11708,6 @@ define <8 x double> @mgather_baseidx_sext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
; RV64ZVE32F-NEXT: andi a2, a2, -128
; RV64ZVE32F-NEXT: beqz a2, .LBB94_13
; RV64ZVE32F-NEXT: # %bb.12: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
@@ -11770,7 +11731,6 @@ define <8 x double> @mgather_baseidx_sext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
; RV64ZVE32F-NEXT: andi a3, a2, 8
; RV64ZVE32F-NEXT: beqz a3, .LBB94_6
; RV64ZVE32F-NEXT: .LBB94_15: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 3
@@ -11779,7 +11739,6 @@ define <8 x double> @mgather_baseidx_sext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
; RV64ZVE32F-NEXT: andi a3, a2, 16
; RV64ZVE32F-NEXT: beqz a3, .LBB94_7
; RV64ZVE32F-NEXT: .LBB94_16: # %cond.load10
-; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-NEXT: slli a3, a3, 3
; RV64ZVE32F-NEXT: add a3, a1, a3
@@ -11948,7 +11907,6 @@ define <8 x double> @mgather_baseidx_zext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
; RV64ZVE32F-NEXT: andi a3, a2, 32
; RV64ZVE32F-NEXT: beqz a3, .LBB95_9
; RV64ZVE32F-NEXT: .LBB95_8: # %cond.load13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 32
@@ -11956,7 +11914,6 @@ define <8 x double> @mgather_baseidx_zext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
; RV64ZVE32F-NEXT: add a3, a1, a3
; RV64ZVE32F-NEXT: fld fa5, 0(a3)
; RV64ZVE32F-NEXT: .LBB95_9: # %else14
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: andi a3, a2, 64
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2
; RV64ZVE32F-NEXT: beqz a3, .LBB95_11
@@ -11970,7 +11927,6 @@ define <8 x double> @mgather_baseidx_zext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
; RV64ZVE32F-NEXT: andi a2, a2, -128
; RV64ZVE32F-NEXT: beqz a2, .LBB95_13
; RV64ZVE32F-NEXT: # %bb.12: # %cond.load19
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 32
@@ -11996,7 +11952,6 @@ define <8 x double> @mgather_baseidx_zext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
; RV64ZVE32F-NEXT: andi a3, a2, 8
; RV64ZVE32F-NEXT: beqz a3, .LBB95_6
; RV64ZVE32F-NEXT: .LBB95_15: # %cond.load7
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a3, v8
; RV64ZVE32F-NEXT: slli a3, a3, 32
@@ -12006,7 +11961,6 @@ define <8 x double> @mgather_baseidx_zext_v8i32_v8f64(ptr %base, <8 x i32> %idxs
; RV64ZVE32F-NEXT: andi a3, a2, 16
; RV64ZVE32F-NEXT: beqz a3, .LBB95_7
; RV64ZVE32F-NEXT: .LBB95_16: # %cond.load10
-; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a3, v10
; RV64ZVE32F-NEXT: slli a3, a3, 32
; RV64ZVE32F-NEXT: srli a3, a3, 29
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
index 5b08fe87bbde..8dad90ef0ba9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
@@ -3687,7 +3687,6 @@ define void @mscatter_baseidx_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8> %id
; RV64ZVE32F-NEXT: andi a0, a4, -128
; RV64ZVE32F-NEXT: beqz a0, .LBB42_12
; RV64ZVE32F-NEXT: .LBB42_16: # %cond.store13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 3
@@ -3934,7 +3933,6 @@ define void @mscatter_baseidx_sext_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: andi a0, a4, -128
; RV64ZVE32F-NEXT: beqz a0, .LBB43_12
; RV64ZVE32F-NEXT: .LBB43_16: # %cond.store13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 3
@@ -4189,7 +4187,6 @@ define void @mscatter_baseidx_zext_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8
; RV64ZVE32F-NEXT: andi a0, a4, -128
; RV64ZVE32F-NEXT: beqz a0, .LBB44_12
; RV64ZVE32F-NEXT: .LBB44_16: # %cond.store13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: andi a0, a0, 255
@@ -4439,7 +4436,6 @@ define void @mscatter_baseidx_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i16> %
; RV64ZVE32F-NEXT: andi a0, a4, -128
; RV64ZVE32F-NEXT: beqz a0, .LBB45_12
; RV64ZVE32F-NEXT: .LBB45_16: # %cond.store13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 3
@@ -4687,7 +4683,6 @@ define void @mscatter_baseidx_sext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: andi a0, a4, -128
; RV64ZVE32F-NEXT: beqz a0, .LBB46_12
; RV64ZVE32F-NEXT: .LBB46_16: # %cond.store13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 3
@@ -4945,7 +4940,6 @@ define void @mscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: andi a0, a5, -128
; RV64ZVE32F-NEXT: beqz a0, .LBB47_12
; RV64ZVE32F-NEXT: .LBB47_16: # %cond.store13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: and a0, a0, a4
@@ -5146,14 +5140,12 @@ define void @mscatter_baseidx_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i32> %
; RV64ZVE32F-NEXT: andi a0, a4, 32
; RV64ZVE32F-NEXT: beqz a0, .LBB48_9
; RV64ZVE32F-NEXT: .LBB48_8: # %cond.store9
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a5, 0(a0)
; RV64ZVE32F-NEXT: .LBB48_9: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: andi a0, a4, 64
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2
; RV64ZVE32F-NEXT: bnez a0, .LBB48_15
@@ -5170,7 +5162,6 @@ define void @mscatter_baseidx_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i32> %
; RV64ZVE32F-NEXT: andi a0, a4, 8
; RV64ZVE32F-NEXT: beqz a0, .LBB48_6
; RV64ZVE32F-NEXT: .LBB48_13: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 3
@@ -5179,7 +5170,6 @@ define void @mscatter_baseidx_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i32> %
; RV64ZVE32F-NEXT: andi a0, a4, 16
; RV64ZVE32F-NEXT: beqz a0, .LBB48_7
; RV64ZVE32F-NEXT: .LBB48_14: # %cond.store7
-; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a0, v10
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
@@ -5195,7 +5185,6 @@ define void @mscatter_baseidx_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i32> %
; RV64ZVE32F-NEXT: andi a0, a4, -128
; RV64ZVE32F-NEXT: beqz a0, .LBB48_11
; RV64ZVE32F-NEXT: .LBB48_16: # %cond.store13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 3
@@ -5394,14 +5383,12 @@ define void @mscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: andi a0, a4, 32
; RV64ZVE32F-NEXT: beqz a0, .LBB49_9
; RV64ZVE32F-NEXT: .LBB49_8: # %cond.store9
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a5, 0(a0)
; RV64ZVE32F-NEXT: .LBB49_9: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: andi a0, a4, 64
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2
; RV64ZVE32F-NEXT: bnez a0, .LBB49_15
@@ -5418,7 +5405,6 @@ define void @mscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: andi a0, a4, 8
; RV64ZVE32F-NEXT: beqz a0, .LBB49_6
; RV64ZVE32F-NEXT: .LBB49_13: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 3
@@ -5427,7 +5413,6 @@ define void @mscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: andi a0, a4, 16
; RV64ZVE32F-NEXT: beqz a0, .LBB49_7
; RV64ZVE32F-NEXT: .LBB49_14: # %cond.store7
-; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a0, v10
; RV64ZVE32F-NEXT: slli a0, a0, 3
; RV64ZVE32F-NEXT: add a0, a1, a0
@@ -5443,7 +5428,6 @@ define void @mscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: andi a0, a4, -128
; RV64ZVE32F-NEXT: beqz a0, .LBB49_11
; RV64ZVE32F-NEXT: .LBB49_16: # %cond.store13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 3
@@ -5645,7 +5629,6 @@ define void @mscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: andi a0, a4, 32
; RV64ZVE32F-NEXT: beqz a0, .LBB50_9
; RV64ZVE32F-NEXT: .LBB50_8: # %cond.store9
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 32
@@ -5653,7 +5636,6 @@ define void @mscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: add a0, a1, a0
; RV64ZVE32F-NEXT: sd a5, 0(a0)
; RV64ZVE32F-NEXT: .LBB50_9: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: andi a0, a4, 64
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2
; RV64ZVE32F-NEXT: bnez a0, .LBB50_15
@@ -5671,7 +5653,6 @@ define void @mscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: andi a0, a4, 8
; RV64ZVE32F-NEXT: beqz a0, .LBB50_6
; RV64ZVE32F-NEXT: .LBB50_13: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 32
@@ -5681,7 +5662,6 @@ define void @mscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: andi a0, a4, 16
; RV64ZVE32F-NEXT: beqz a0, .LBB50_7
; RV64ZVE32F-NEXT: .LBB50_14: # %cond.store7
-; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a0, v10
; RV64ZVE32F-NEXT: slli a0, a0, 32
; RV64ZVE32F-NEXT: srli a0, a0, 29
@@ -5699,7 +5679,6 @@ define void @mscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV64ZVE32F-NEXT: andi a0, a4, -128
; RV64ZVE32F-NEXT: beqz a0, .LBB50_11
; RV64ZVE32F-NEXT: .LBB50_16: # %cond.store13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 32
@@ -8770,7 +8749,6 @@ define void @mscatter_baseidx_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x i8>
; RV64ZVE32F-NEXT: andi a1, a1, -128
; RV64ZVE32F-NEXT: beqz a1, .LBB81_12
; RV64ZVE32F-NEXT: .LBB81_16: # %cond.store13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: slli a1, a1, 3
@@ -8973,7 +8951,6 @@ define void @mscatter_baseidx_sext_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: andi a1, a1, -128
; RV64ZVE32F-NEXT: beqz a1, .LBB82_12
; RV64ZVE32F-NEXT: .LBB82_16: # %cond.store13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: slli a1, a1, 3
@@ -9184,7 +9161,6 @@ define void @mscatter_baseidx_zext_v8i8_v8f64(<8 x double> %val, ptr %base, <8 x
; RV64ZVE32F-NEXT: andi a1, a1, -128
; RV64ZVE32F-NEXT: beqz a1, .LBB83_12
; RV64ZVE32F-NEXT: .LBB83_16: # %cond.store13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: andi a1, a1, 255
@@ -9390,7 +9366,6 @@ define void @mscatter_baseidx_v8i16_v8f64(<8 x double> %val, ptr %base, <8 x i16
; RV64ZVE32F-NEXT: andi a1, a1, -128
; RV64ZVE32F-NEXT: beqz a1, .LBB84_12
; RV64ZVE32F-NEXT: .LBB84_16: # %cond.store13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: slli a1, a1, 3
@@ -9594,7 +9569,6 @@ define void @mscatter_baseidx_sext_v8i16_v8f64(<8 x double> %val, ptr %base, <8
; RV64ZVE32F-NEXT: andi a1, a1, -128
; RV64ZVE32F-NEXT: beqz a1, .LBB85_12
; RV64ZVE32F-NEXT: .LBB85_16: # %cond.store13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: slli a1, a1, 3
@@ -9808,7 +9782,6 @@ define void @mscatter_baseidx_zext_v8i16_v8f64(<8 x double> %val, ptr %base, <8
; RV64ZVE32F-NEXT: andi a2, a2, -128
; RV64ZVE32F-NEXT: beqz a2, .LBB86_12
; RV64ZVE32F-NEXT: .LBB86_16: # %cond.store13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: and a1, a2, a1
@@ -9965,14 +9938,12 @@ define void @mscatter_baseidx_v8i32_v8f64(<8 x double> %val, ptr %base, <8 x i32
; RV64ZVE32F-NEXT: andi a2, a1, 32
; RV64ZVE32F-NEXT: beqz a2, .LBB87_9
; RV64ZVE32F-NEXT: .LBB87_8: # %cond.store9
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa5, 0(a2)
; RV64ZVE32F-NEXT: .LBB87_9: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: andi a2, a1, 64
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2
; RV64ZVE32F-NEXT: bnez a2, .LBB87_15
@@ -9989,7 +9960,6 @@ define void @mscatter_baseidx_v8i32_v8f64(<8 x double> %val, ptr %base, <8 x i32
; RV64ZVE32F-NEXT: andi a2, a1, 8
; RV64ZVE32F-NEXT: beqz a2, .LBB87_6
; RV64ZVE32F-NEXT: .LBB87_13: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
@@ -9998,7 +9968,6 @@ define void @mscatter_baseidx_v8i32_v8f64(<8 x double> %val, ptr %base, <8 x i32
; RV64ZVE32F-NEXT: andi a2, a1, 16
; RV64ZVE32F-NEXT: beqz a2, .LBB87_7
; RV64ZVE32F-NEXT: .LBB87_14: # %cond.store7
-; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -10014,7 +9983,6 @@ define void @mscatter_baseidx_v8i32_v8f64(<8 x double> %val, ptr %base, <8 x i32
; RV64ZVE32F-NEXT: andi a1, a1, -128
; RV64ZVE32F-NEXT: beqz a1, .LBB87_11
; RV64ZVE32F-NEXT: .LBB87_16: # %cond.store13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: slli a1, a1, 3
@@ -10169,14 +10137,12 @@ define void @mscatter_baseidx_sext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
; RV64ZVE32F-NEXT: andi a2, a1, 32
; RV64ZVE32F-NEXT: beqz a2, .LBB88_9
; RV64ZVE32F-NEXT: .LBB88_8: # %cond.store9
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa5, 0(a2)
; RV64ZVE32F-NEXT: .LBB88_9: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: andi a2, a1, 64
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2
; RV64ZVE32F-NEXT: bnez a2, .LBB88_15
@@ -10193,7 +10159,6 @@ define void @mscatter_baseidx_sext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
; RV64ZVE32F-NEXT: andi a2, a1, 8
; RV64ZVE32F-NEXT: beqz a2, .LBB88_6
; RV64ZVE32F-NEXT: .LBB88_13: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 3
@@ -10202,7 +10167,6 @@ define void @mscatter_baseidx_sext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
; RV64ZVE32F-NEXT: andi a2, a1, 16
; RV64ZVE32F-NEXT: beqz a2, .LBB88_7
; RV64ZVE32F-NEXT: .LBB88_14: # %cond.store7
-; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 3
; RV64ZVE32F-NEXT: add a2, a0, a2
@@ -10218,7 +10182,6 @@ define void @mscatter_baseidx_sext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
; RV64ZVE32F-NEXT: andi a1, a1, -128
; RV64ZVE32F-NEXT: beqz a1, .LBB88_11
; RV64ZVE32F-NEXT: .LBB88_16: # %cond.store13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: slli a1, a1, 3
@@ -10376,7 +10339,6 @@ define void @mscatter_baseidx_zext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
; RV64ZVE32F-NEXT: andi a2, a1, 32
; RV64ZVE32F-NEXT: beqz a2, .LBB89_9
; RV64ZVE32F-NEXT: .LBB89_8: # %cond.store9
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 32
@@ -10384,7 +10346,6 @@ define void @mscatter_baseidx_zext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
; RV64ZVE32F-NEXT: add a2, a0, a2
; RV64ZVE32F-NEXT: fsd fa5, 0(a2)
; RV64ZVE32F-NEXT: .LBB89_9: # %else10
-; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: andi a2, a1, 64
; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2
; RV64ZVE32F-NEXT: bnez a2, .LBB89_15
@@ -10402,7 +10363,6 @@ define void @mscatter_baseidx_zext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
; RV64ZVE32F-NEXT: andi a2, a1, 8
; RV64ZVE32F-NEXT: beqz a2, .LBB89_6
; RV64ZVE32F-NEXT: .LBB89_13: # %cond.store5
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a2, v8
; RV64ZVE32F-NEXT: slli a2, a2, 32
@@ -10412,7 +10372,6 @@ define void @mscatter_baseidx_zext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
; RV64ZVE32F-NEXT: andi a2, a1, 16
; RV64ZVE32F-NEXT: beqz a2, .LBB89_7
; RV64ZVE32F-NEXT: .LBB89_14: # %cond.store7
-; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a2, v10
; RV64ZVE32F-NEXT: slli a2, a2, 32
; RV64ZVE32F-NEXT: srli a2, a2, 29
@@ -10430,7 +10389,6 @@ define void @mscatter_baseidx_zext_v8i32_v8f64(<8 x double> %val, ptr %base, <8
; RV64ZVE32F-NEXT: andi a1, a1, -128
; RV64ZVE32F-NEXT: beqz a1, .LBB89_11
; RV64ZVE32F-NEXT: .LBB89_16: # %cond.store13
-; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: slli a1, a1, 32
diff --git a/llvm/test/CodeGen/RISCV/rvv/fold-vector-cmp.ll b/llvm/test/CodeGen/RISCV/rvv/fold-vector-cmp.ll
index d873d9ad7c85..db2361dd3e58 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fold-vector-cmp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fold-vector-cmp.ll
@@ -20,7 +20,6 @@ define i32 @test(i32 %call.i) {
; CHECK-V-NEXT: vmslt.vx v0, v8, a0
; CHECK-V-NEXT: vmv.v.i v8, 0
; CHECK-V-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-V-NEXT: vslidedown.vi v8, v8, 1
; CHECK-V-NEXT: vmv.x.s a0, v8
; CHECK-V-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
index 4a6f52ac940b..9e8463a08530 100644
--- a/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
@@ -22,9 +22,7 @@ define <4 x i8> @v2i8_2(<2 x i8> %a, <2 x i8> %b) {
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vslideup.vi v10, v8, 1
-; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v9, 1
-; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2
@@ -172,9 +170,7 @@ define <4 x i16> @v2i16_2(<2 x i16> %a, <2 x i16> %b) {
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v10, v8, 1
-; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v9, 1
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2
@@ -321,9 +317,7 @@ define <4 x i32> @v2i32_2(<2 x i32> %a, < 2 x i32> %b) {
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v10, v8, 1
-; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v9, 1
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2
@@ -471,9 +465,7 @@ define <4 x i64> @v2i64_2(<2 x i64> %a, < 2 x i64> %b) {
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vslideup.vi v10, v8, 1
-; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v9, 1
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2
@@ -560,9 +552,7 @@ define <4 x half> @v2f16_2(<2 x half> %a, <2 x half> %b) {
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v10, v8, 1
-; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v9, 1
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2
@@ -683,9 +673,7 @@ define <4 x float> @v2f32_2(<2 x float> %a, <2 x float> %b) {
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v10, v8, 1
-; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v9, 1
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2
@@ -776,9 +764,7 @@ define <4 x double> @v2f64_2(<2 x double> %a, < 2 x double> %b) {
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vslideup.vi v10, v8, 1
-; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v9, 1
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll b/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
index 6faa4f6b45da..67431f72c9cc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
@@ -15,9 +15,7 @@ define <vscale x 1 x i1> @splice_nxv1i1_offset_negone(<vscale x 1 x i1> %a, <vsc
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vslidedown.vx v10, v10, a0
-; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v8, v9, 1, v0
; CHECK-NEXT: vslideup.vi v10, v8, 1
@@ -61,9 +59,7 @@ define <vscale x 2 x i1> @splice_nxv2i1_offset_negone(<vscale x 2 x i1> %a, <vsc
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v10, v10, a0
-; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v8, v9, 1, v0
; CHECK-NEXT: vslideup.vi v10, v8, 1
@@ -107,9 +103,7 @@ define <vscale x 4 x i1> @splice_nxv4i1_offset_negone(<vscale x 4 x i1> %a, <vsc
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v10, v10, a0
-; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v8, v9, 1, v0
; CHECK-NEXT: vslideup.vi v10, v8, 1
@@ -152,9 +146,7 @@ define <vscale x 8 x i1> @splice_nxv8i1_offset_negone(<vscale x 8 x i1> %a, <vsc
; CHECK-NEXT: vmerge.vim v10, v9, 1, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v10, v10, a0
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v8, v9, 1, v0
; CHECK-NEXT: vslideup.vi v10, v8, 1
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll b/llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll
index b069d2fceeb7..7b8c2ae3e29b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll
@@ -198,11 +198,9 @@ define <vscale x 4 x i1> @splat_idx_nxv4i32(<vscale x 4 x i1> %v, i64 %idx) {
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: andi a0, a0, 1
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll b/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
index 2fa8474858c0..dceae00d2e51 100644
--- a/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
@@ -564,7 +564,6 @@ define void @test_urem_vec(ptr %X) nounwind {
; RV32MV-NEXT: vand.vx v8, v8, a1
; RV32MV-NEXT: vmsltu.vv v0, v12, v8
; RV32MV-NEXT: vmerge.vim v8, v10, -1, v0
-; RV32MV-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV32MV-NEXT: vslidedown.vi v9, v8, 2
; RV32MV-NEXT: vmv.x.s a1, v9
; RV32MV-NEXT: slli a2, a1, 21
@@ -628,7 +627,6 @@ define void @test_urem_vec(ptr %X) nounwind {
; RV64MV-NEXT: vmerge.vim v8, v10, -1, v0
; RV64MV-NEXT: vmv.x.s a1, v8
; RV64MV-NEXT: andi a1, a1, 2047
-; RV64MV-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64MV-NEXT: vslidedown.vi v9, v8, 1
; RV64MV-NEXT: vmv.x.s a2, v9
; RV64MV-NEXT: andi a2, a2, 2047
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