[PATCH] D150177: [RISCV] Enable signed truncation check transforms for i8

[Yingwei Zheng via Phabricator via llvm-commits]

dtcxzyw added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/lack-of-signed-truncation-check.ll:401
+; RV32I-NEXT:    sltu a0, a2, a0
+; RV32I-NEXT:    add a0, a1, a0
+; RV32I-NEXT:    addi a0, a0, -1
----------------
reames wrote:
> These two instructions are an odd variant of the add-carry from below.  This looks like something got turned into a select whereas the add-with-carry + compare-two-halves should have worked here.
After legalization, RISCVISD::SELECT_CC was created. Then It was lowered to Select_GPR_Using_CC_GPR at the end of ISel.
```
Legalized selection DAG: %bb.0
SelectionDAG has 21 nodes:	
  t0: ch,glue = EntryToken	
  t2: i32,ch = CopyFromReg t0, Register:i32 %0	
  t20: i32 = add t2, Constant:i32<-128>	
      t4: i32,ch = CopyFromReg t0, Register:i32 %1	
      t22: i32 = setcc t20, t2, setult:ch	
    t33: i32 = add t4, t22	
  t34: i32 = add t33, Constant:i32<-1>	
      t27: i32 = setcc t20, Constant:i32<-256>, setult:ch	
      t29: i32 = setcc t34, Constant:i32<-1>, setne:ch	
    t35: i32 = RISCVISD::SELECT_CC t34, Constant:i32<-1>, seteq:ch, t27, t29	
  t13: ch,glue = CopyToReg t0, Register:i32 $x10, t35	
  t14: ch = RISCVISD::RET_GLUE t13, Register:i32 $x10, t13:1
===== Instruction selection ends:	
Selected selection DAG: %bb.0
SelectionDAG has 21 nodes:	
  t0: ch,glue = EntryToken	
  t2: i32,ch = CopyFromReg t0, Register:i32 %0	
  t20: i32 = ADDI t2, TargetConstant:i32<-128>	
      t4: i32,ch = CopyFromReg t0, Register:i32 %1	
      t22: i32 = SLTU t20, t2	
    t33: i32 = ADD t4, t22	
  t34: i32 = ADDI t33, TargetConstant:i32<-1>	
      t41: i32 = ADDI Register:i32 $x0, TargetConstant:i32<-1>	
      t27: i32 = SLTIU t20, TargetConstant:i32<-256>	
      t29: i32 = SLTIU t34, TargetConstant:i32<-1>	
    t35: i32 = Select_GPR_Using_CC_GPR t34, t41, TargetConstant:i32<0>, t27, t29	
  t13: ch,glue = CopyToReg t0, Register:i32 $x10, t35	
  t14: ch = PseudoRET Register:i32 $x10, t13, t13:1
```
In this case, we can fold (riscvisd::select_cc lhs, rhs, cc, truev, (setcc lhs, rhs, inv cc)) into (riscvisd::select_cc lhs, rhs, cc, truev, 1) and eventually into (or (setcc lhs, rhs, inv cc), truev).
I will try to improve the code without Zbb in follow-up patches.



Repository:
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  https://reviews.llvm.org/D150177/new/

https://reviews.llvm.org/D150177