[PATCH] D149260: [AArch64] Emit FNMADD instead of FNEG(FMADD)

[Matt Devereau via Phabricator via llvm-commits]

MattDevereau marked 3 inline comments as done.
MattDevereau added inline comments.


================
Comment at: llvm/include/llvm/CodeGen/MachineCombinerPattern.h:182-183
+
+  FNMADDS,
+  FNMADDD,
 };
----------------
MattDevereau wrote:
> sdesmalen wrote:
> > Having two patterns, one for 32-bit values, and one for 64-bit values doesn't match what was done for FMSUB/FNMSUB. Can these be merged into 1 and use the register class used for the operands to determine which instruction to use?
> I'm not sure what you mean? MachineCombinerPattern::FNMSUB isn't used in  `AArch64InstrInfo::genAlternativeCodeSequence` at all. The way FNMSUB is combined in this function has `MachineCombinerPattern::FMULSUBH_OP1` `MachineCombinerPattern::FMULSUBS_OP1` and `MachineCombinerPattern::FMULSUBD_OP1:` which all describe the number of bits. I'd need to do something like
> 
> 
> ```
> auto RC = MRI.getRegClass(MAD->getOperand(0).getReg());
> if RC == 64bit
>   opc = FNMADDDrrr
> else if RC == 32bit
>   opc = FNMADDSrrr
> ```
> which I can't see a clear example of
I managed to achieve this with `Arch64::FPR32RegClass.hasSubClassEq(RC)` in the end


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https://reviews.llvm.org/D149260