[PATCH] D149916: [VP][SelectionDAG][RISCV] Add get_vector_length intrinsics and generic SelectionDAG support.

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue May 9 11:16:14 PDT 2023


craig.topper updated this revision to Diff 520761.
craig.topper added a comment.

-Add SVE test.
-Updates to LangRef. Reflect that this intrinsic is not require to return VF*vscale for count > VF*vscale. We need this to make RISC-V's vsetvli a valid implementation of this intrinsic.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149916/new/

https://reviews.llvm.org/D149916

Files:
  llvm/docs/LangRef.rst
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/include/llvm/IR/Intrinsics.td
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/test/CodeGen/AArch64/get_vector_length.ll
  llvm/test/CodeGen/RISCV/rvv/get_vector_length.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D149916.520761.patch
Type: text/x-patch
Size: 8750 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230509/bc9777c5/attachment.bin>


More information about the llvm-commits mailing list