[PATCH] D149743: [RISCV][CodeGen] Support Zdinx on RV32 codegen

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:291
+      BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI),
+              MBBI->getOperand(1).getReg())
+          .addReg(MBBI->getOperand(1).getReg(),
----------------
As I said before, we can't modify the operand 1 register if it is used after the store.


================
Comment at: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:321
+    BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
+        .add(MBBI->getOperand(1))
+        .add(MBBI->getOperand(2));
----------------
Lo could be the same register as operand 1, in which case you can't use it here because it was overwritten.


================
Comment at: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp:278
+    assert(MBBI->getOperand(2).getOffset() == 0);
+    MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
+    BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
----------------
liaolucy wrote:
> craig.topper wrote:
> > craig.topper wrote:
> > > This doesn't work. The load/store is paired with an LUI. The offset in the LUI needs to match. This just moved the overflow to the linker.
> > I guess if the global is 8 byte aligned, the +4 won't cause any wrap.
> The current test affected by this code is fld_fsd_global in double-mem.ll. 
f64 loads are not guaranteed to be a 8 byte aligned the unaligned-scalar-mem subtarget feature is used.


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https://reviews.llvm.org/D149743