[PATCH] D141485: [X86] Add schedule module for SapphireRapids

Mon May 8 20:59:22 PDT 2023

HaohaiWen added a comment.

In D141485#4327309 <https://reviews.llvm.org/D141485#4327309>, @goldstein.w.n wrote:

> In D141485#4043332 <https://reviews.llvm.org/D141485#4043332>, @HaohaiWen wrote:
>
>> Instruction's scheduling info in this model comes from many sources.
>> Priority of source is (dsc order)
>>
>> 1. 4th Generation Intel® Xeon® Scalable Processor Family (based on Sapphire Rapids Architecture) Instruction Throughput and Latency in https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html
>> 2. Alderlake-P data from uops.info
>> 3. Current SkylakeServerModel.
>
> Why skylake server as opposed to ICX server?

The priority is:

1. Alderlake-P data (including avx512) from uops.info
2. 4th Generation Intel® Xeon® Scalable Processor Family (based on Sapphire Rapids Architecture) Instruction Throughput and Latency in https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html
3. Current IcelakeModel.

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D141485/new/

https://reviews.llvm.org/D141485