[PATCH] D150098: [DAGCombiner] Improve `computeKnownBits` implementations of `sdiv` and `udiv`

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n updated this revision to Diff 520567.
goldstein.w.n added a comment.

Causes regression in ARM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150098/new/

https://reviews.llvm.org/D150098

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/test/CodeGen/ARM/select-imm.ll
  llvm/test/CodeGen/X86/knownbits-div.ll


Index: llvm/test/CodeGen/X86/knownbits-div.ll
===================================================================
--- llvm/test/CodeGen/X86/knownbits-div.ll
+++ llvm/test/CodeGen/X86/knownbits-div.ll
@@ -4,11 +4,7 @@
 define i8 @sdiv_neg_neg_high_bits(i8 %x, i8 %y) {
 ; CHECK-LABEL: sdiv_neg_neg_high_bits:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    orb $-128, %dil
-; CHECK-NEXT:    orb $-125, %sil
-; CHECK-NEXT:    movsbl %dil, %eax
-; CHECK-NEXT:    idivb %sil
-; CHECK-NEXT:    andb $-128, %al
+; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    retq
   %num = or i8 %x, 128
   %denum = or i8 %y, 131
@@ -20,11 +16,7 @@
 define i8 @sdiv_exact_odd_odd(i8 %x, i8 %y) {
 ; CHECK-LABEL: sdiv_exact_odd_odd:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    orb $1, %dil
-; CHECK-NEXT:    orb $1, %sil
-; CHECK-NEXT:    movsbl %dil, %eax
-; CHECK-NEXT:    idivb %sil
-; CHECK-NEXT:    andb $1, %al
+; CHECK-NEXT:    movb $1, %al
 ; CHECK-NEXT:    retq
   %num = or i8 %x, 1
   %denum = or i8 %y, 1
@@ -52,11 +44,7 @@
 define i8 @udiv_exact_even_odd(i8 %x, i8 %y) {
 ; CHECK-LABEL: udiv_exact_even_odd:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    andb $-2, %dil
-; CHECK-NEXT:    orb $1, %sil
-; CHECK-NEXT:    movzbl %dil, %eax
-; CHECK-NEXT:    divb %sil
-; CHECK-NEXT:    andb $1, %al
+; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    retq
   %num = and i8 %x, -2
   %denum = or i8 %y, 1
Index: llvm/test/CodeGen/ARM/select-imm.ll
===================================================================
--- llvm/test/CodeGen/ARM/select-imm.ll
+++ llvm/test/CodeGen/ARM/select-imm.ll
@@ -657,9 +657,12 @@
 ; V8MBASE-NEXT:    movs r0, #7
 ; V8MBASE-NEXT:    mvns r0, r0
 ; V8MBASE-NEXT:    str r0, [sp]
-; V8MBASE-NEXT:    adds r0, r0, #5
-; V8MBASE-NEXT:    str r0, [sp, #4]
-; V8MBASE-NEXT:    movs r1, #0
+; V8MBASE-NEXT:    adds r1, r0, #5
+; V8MBASE-NEXT:    str r1, [sp, #4]
+; V8MBASE-NEXT:    sdiv r2, r1, r0
+; V8MBASE-NEXT:    muls r2, r0, r2
+; V8MBASE-NEXT:    subs r0, r1, r2
+; V8MBASE-NEXT:    subs r1, r0, r1
 ; V8MBASE-NEXT:    rsbs r0, r1, #0
 ; V8MBASE-NEXT:    adcs r0, r1
 ; V8MBASE-NEXT:    add sp, #8
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -3703,7 +3703,13 @@
   case ISD::UDIV: {
     Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
     Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
-    Known = KnownBits::udiv(Known, Known2);
+    Known = KnownBits::udiv(Known, Known2, Op->getFlags().hasExact());
+    break;
+  }
+  case ISD::SDIV: {
+    Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
+    Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
+    Known = KnownBits::sdiv(Known, Known2, Op->getFlags().hasExact());
     break;
   }
   case ISD::SREM: {


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