[PATCH] D149811: [RISCV][CodeGen] Support Zhinx and Zhinxmin

[QIHAN CAI via Phabricator via llvm-commits]

realqhc added a comment.

In D149811#4328349 <https://reviews.llvm.org/D149811#4328349>, @realqhc wrote:

> In D149811#4328339 <https://reviews.llvm.org/D149811#4328339>, @craig.topper wrote:
>
>> Do we need to update `RISCVInstrInfo::storeRegToStackSlot` and RISCVInstrInfo::loadRegFromStackSlot`?
>
> Based on my understanding, it may not require update, as the GPRRegClass load and store is handling it similar to the zfinx patch.



  Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  <+>UTF-8
  ===================================================================
  diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp	(revision e87fdd6d05cdcb47a9019aea13985cee543a57e4)
  +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp	(date 1683595013203)
  @@ -522,6 +522,9 @@
       Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
                RISCV::SW : RISCV::SD;
       IsScalableVector = false;
  +  } else if (RISCV::GPRF16RegClass.hasSubClassEq(RC)) {
  +    Opcode = RISCV::SH;
  +    IsScalableVector = false;
     } else if (RISCV::GPRPF64RegClass.hasSubClassEq(RC)) {
       Opcode = RISCV::PseudoRV32ZdinxSD;
       IsScalableVector = false;
  @@ -610,6 +613,9 @@
     if (RISCV::GPRRegClass.hasSubClassEq(RC)) {
       Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
                RISCV::LW : RISCV::LD;
  +    IsScalableVector = false;
  +  } else if (RISCV::GPRF16RegClass.hasSubClassEq(RC)) {
  +    Opcode = RISCV::LH;
       IsScalableVector = false;
     } else if (RISCV::GPRPF64RegClass.hasSubClassEq(RC)) {
       Opcode = RISCV::PseudoRV32ZdinxLD;

This patch does not incur change on the test.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D149811/new/

https://reviews.llvm.org/D149811