[PATCH] D149811: [RISCV][CodeGen] Support Zhinx and Zhinxmin
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon May 8 18:05:03 PDT 2023
craig.topper added a comment.
In D149811#4328349 <https://reviews.llvm.org/D149811#4328349>, @realqhc wrote:
> In D149811#4328339 <https://reviews.llvm.org/D149811#4328339>, @craig.topper wrote:
>
>> Do we need to update `RISCVInstrInfo::storeRegToStackSlot` and RISCVInstrInfo::loadRegFromStackSlot`?
>
> Based on my understanding, it may not require update, as the GPRRegClass load and store is handling it similar to the zfinx patch.
I hadn't noticed we are using the same spill sizes for GPRF16/GPRF32/GPRF64. So you're correct it doesn't need an update.
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