[PATCH] D149811: [RISCV][CodeGen] Support Zhinx and Zhinxmin

[QIHAN CAI via Phabricator via llvm-commits]

realqhc added a comment.

In D149811#4328339 <https://reviews.llvm.org/D149811#4328339>, @craig.topper wrote:

> Do we need to update `RISCVInstrInfo::storeRegToStackSlot` and RISCVInstrInfo::loadRegFromStackSlot`?

Based on my understanding, it may not require update, as the GPRRegClass load and store is handling it similar to the zfinx patch.


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