[PATCH] D150125: [AArch64][SVE] Custom ISelLowering for 256b `shuffle_vector v, undef, <1, 0, 1, 0>`

[Cameron McInally via Phabricator via llvm-commits]

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Continuing from D149749 <https://reviews.llvm.org/D149749>, here is another neoverse-v1 VLS shuffle that could be lowered better...

%x = shufflevector <2 x double> %v, <2 x double> poison, <4 x i32> <i32 1, i32 0, i32 1, i32 0>

It could be lowered in a number of ways, but I chose:

zip1 z0.d, z0.d, z0.d
uzp1 z0.d, z0.d, z0.d
ext z0.b, z0.b, z0.b, #8

The new lowering shows a 9% performance boost on 538.namd with our out-of-tree compiler.

Note that this solution takes 6 cycles, compared to a NEON sequence at 4 cycles. This is unfortunate, but I could not find a faster SVE sequence for this shuffle. [Maybe a better solution is to fall back to NEON for shuffles of this form?]


https://reviews.llvm.org/D150125

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle.ll

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