[llvm] 6b99628 - [X86][CodeGen] Do not add `offset` for memory reference using symbol
Alvin Wong via llvm-commits
llvm-commits at lists.llvm.org
Mon May 8 09:08:09 PDT 2023
Author: Alvin Wong
Date: 2023-05-09T00:07:40+08:00
New Revision: 6b996282cee3588e46b18c30957e71c964012e14
URL: https://github.com/llvm/llvm-project/commit/6b996282cee3588e46b18c30957e71c964012e14
DIFF: https://github.com/llvm/llvm-project/commit/6b996282cee3588e46b18c30957e71c964012e14.diff
LOG: [X86][CodeGen] Do not add `offset` for memory reference using symbol
In the past, D71436 added writing the `offset` operator for some
legitimate cases. However, for memory references in Intel syntax, the
`offset` operator (`[offset sym]`) appears to be superfluous at best,
possibly wrong and contradictory at worst.
This patch bypasses writing the `offset` operator in
`X86AsmPrinter::PrintIntelMemReference` which affects exactly this
case. A similar code flow exists in `X86IntelInstPrinter.cpp` -
`X86IntelInstPrinter::printMemReference`.
The motivation for fixing this output is to allow us to reject the
confusing `call [offset fn_ref]` syntax in MC, as discussed in D149579.
Depends on D149579
Differential Revision: https://reviews.llvm.org/D150047
Added:
llvm/test/CodeGen/X86/ms-inline-asm-functions.ll
Modified:
llvm/lib/Target/X86/X86AsmPrinter.cpp
llvm/test/CodeGen/X86/ms-inline-asm.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86AsmPrinter.cpp b/llvm/lib/Target/X86/X86AsmPrinter.cpp
index ff1e1eeebc1dd..bb94444525fb8 100644
--- a/llvm/lib/Target/X86/X86AsmPrinter.cpp
+++ b/llvm/lib/Target/X86/X86AsmPrinter.cpp
@@ -510,7 +510,9 @@ void X86AsmPrinter::PrintIntelMemReference(const MachineInstr *MI,
if (!DispSpec.isImm()) {
if (NeedPlus) O << " + ";
- PrintOperand(MI, OpNo + X86::AddrDisp, O);
+ // Do not add `offset` operator. Matches the behaviour of
+ // X86IntelInstPrinter::printMemReference.
+ PrintSymbolOperand(DispSpec, O);
} else {
int64_t DispVal = DispSpec.getImm();
if (DispVal || (!IndexReg.getReg() && !HasBaseReg)) {
diff --git a/llvm/test/CodeGen/X86/ms-inline-asm-functions.ll b/llvm/test/CodeGen/X86/ms-inline-asm-functions.ll
new file mode 100644
index 0000000000000..c7cc7056c85cc
--- /dev/null
+++ b/llvm/test/CodeGen/X86/ms-inline-asm-functions.ll
@@ -0,0 +1,105 @@
+;; Check that the generated memory references do not contain the `offset`
+;; operator. Use `-no-integrated-as` to disable AsmParser formatting.
+; RUN: llc -no-integrated-as -x86-asm-syntax=intel < %s | FileCheck %s
+
+;; This file was compiled from clang/test/CodeGen/ms-inline-asm-functions.c,
+;; using the following command line:
+;;
+;; bin/clang -cc1 -internal-isystem lib/clang/17/include -nostdsysteminc \
+;; ../llvm-project/clang/test/CodeGen/ms-inline-asm-functions.c \
+;; -triple i386-pc-windows-msvc -fms-extensions -S -o out.ll
+
+source_filename = "/llvm-project/clang/test/CodeGen/ms-inline-asm-functions.c"
+target datalayout = "e-m:x-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32-a:0:32-S32"
+target triple = "i386-pc-windows-msvc"
+
+ at kptr = dso_local global ptr null, align 4
+
+; Function Attrs: noinline nounwind optnone
+define dso_local i32 @foo() #0 {
+entry:
+ %r = alloca ptr, align 4
+ %call = call ptr @gptr()
+ store ptr %call, ptr %r, align 4
+ %0 = call i32 asm sideeffect inteldialect "call ${1:P}\0A\09call $2\0A\09call ${3:P}\0A\09call $4", "={eax},*m,*m,*m,*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32 (i32)) @k, ptr elementtype(ptr) %r, ptr elementtype(i32 (i32)) @kimport, ptr elementtype(ptr) @kptr) #3, !srcloc !4
+ ; CHECK-LABEL: _foo:
+ ; CHECK: #APP
+ ; CHECK-NEXT: .intel_syntax
+ ; CHECK-NEXT: call _k
+ ; CHECK-NEXT: call [e{{([a-z]{2})}}]
+ ; CHECK-NEXT: call [e{{([a-z]{2})}}]
+ ; CHECK-NEXT: call [_kptr]
+ ; CHECK-NEXT: .att_syntax
+ ; CHECK-NEXT: #NO_APP
+ ret i32 %0
+}
+
+declare dso_local ptr @gptr()
+
+declare dso_local i32 @k(i32 noundef)
+
+declare dllimport i32 @kimport(i32 noundef)
+
+; Function Attrs: noinline nounwind optnone
+define dso_local i32 @bar() #0 {
+entry:
+ %0 = call i32 asm sideeffect inteldialect "jmp ${1:P}\0A\09ja ${2:P}\0A\09JAE ${3:P}\0A\09LOOP ${4:P}\0A\09loope ${5:P}\0A\09loopne ${6:P}", "={eax},*m,*m,*m,*m,*m,*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32 (i32)) @k, ptr elementtype(i32 (i32)) @k, ptr elementtype(i32 (i32)) @k, ptr elementtype(i32 (i32)) @k, ptr elementtype(i32 (i32)) @k, ptr elementtype(i32 (i32)) @k) #3, !srcloc !5
+ ; CHECK-LABEL: _bar:
+ ; CHECK: #APP
+ ; CHECK-NEXT: .intel_syntax
+ ; CHECK-NEXT: jmp _k
+ ; CHECK-NEXT: ja [_k]
+ ; CHECK-NEXT: JAE [_k]
+ ; CHECK-NEXT: LOOP [_k]
+ ; CHECK-NEXT: loope [_k]
+ ; CHECK-NEXT: loopne [_k]
+ ; CHECK-NEXT: .att_syntax
+ ; CHECK-NEXT: #NO_APP
+ ret i32 %0
+}
+
+; Function Attrs: noinline nounwind optnone
+define dso_local i32 @baz() #0 {
+entry:
+ %0 = call i32 asm sideeffect inteldialect "mov eax, $1\0A\09mov eax, $2", "=&{eax},*m,*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32 (i32)) @k, ptr elementtype(ptr) @kptr) #3, !srcloc !6
+ ; CHECK-LABEL: _baz:
+ ; CHECK: #APP
+ ; CHECK-NEXT: .intel_syntax
+ ; CHECK-NEXT: mov eax, [_k]
+ ; CHECK-NEXT: mov eax, [_kptr]
+ ; CHECK-NEXT: .att_syntax
+ ; CHECK-NEXT: #NO_APP
+ ret i32 %0
+}
+
+; Function Attrs: naked noinline nounwind optnone
+define dso_local void @naked() #2 {
+entry:
+ call void asm sideeffect inteldialect "pusha\0A\09call ${0:P}\0A\09popa\0A\09ret", "*m,~{eax},~{ebp},~{ebx},~{ecx},~{edi},~{edx},~{esi},~{esp},~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32 (i32)) @k) #3, !srcloc !7
+ ; CHECK-LABEL: _naked:
+ ; CHECK: #APP
+ ; CHECK-NEXT: .intel_syntax
+ ; CHECK-NEXT: pusha
+ ; CHECK-NEXT: call _k
+ ; CHECK-NEXT: popa
+ ; CHECK-NEXT: ret
+ ; CHECK-NEXT: .att_syntax
+ ; CHECK-NEXT: #NO_APP
+ unreachable
+}
+
+attributes #0 = { noinline nounwind optnone }
+attributes #2 = { naked noinline nounwind optnone }
+attributes #3 = { nounwind }
+
+!llvm.module.flags = !{!0, !1, !2}
+!llvm.ident = !{!3}
+
+!0 = !{i32 1, !"NumRegisterParameters", i32 0}
+!1 = !{i32 1, !"wchar_size", i32 2}
+!2 = !{i32 1, !"MaxTLSAlign", i32 65536}
+!3 = !{!"clang version 17.0.0"}
+!4 = !{i64 528}
+!5 = !{i64 892}
+!6 = !{i64 1183}
+!7 = !{i64 1451}
diff --git a/llvm/test/CodeGen/X86/ms-inline-asm.ll b/llvm/test/CodeGen/X86/ms-inline-asm.ll
index 2487b9bb6b8d6..ab4f4d540dbe3 100644
--- a/llvm/test/CodeGen/X86/ms-inline-asm.ll
+++ b/llvm/test/CodeGen/X86/ms-inline-asm.ll
@@ -91,7 +91,7 @@ entry:
; CHECK-LABEL: t30:
; CHECK: {{## InlineAsm Start|#APP}}
; CHECK: .intel_syntax
-; CHECK: lea edi, dword ptr [offset {{_?}}results]
+; CHECK: lea edi, dword ptr [{{_?}}results]
; CHECK: .att_syntax
; CHECK: {{## InlineAsm End|#NO_APP}}
; CHECK: {{## InlineAsm Start|#APP}}
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