[PATCH] D150076: Summary: Add support for XAR instruction generation to the AArch64 backend

[Shreyansh Chouhan via Phabricator via llvm-commits]

BK1603 created this revision.
BK1603 added a reviewer: dmgreen.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
BK1603 requested review of this revision.
Herald added a project: LLVM.
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Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D150076

Files:
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/test/CodeGen/AArch64/xar.ll


Index: llvm/test/CodeGen/AArch64/xar.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/xar.ll
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+
+; RUN: llc -mtriple=aarch64-none-eabi -mattr=+sha3 < %s | FileCheck --check-prefix=SHA3 %s
+; RUN: llc -mtriple=aarch64-none-eabi -mattr=-sha3 < %s | FileCheck --check-prefix=NOSHA3 %s
+
+define <2 x i64> @xar_54(<2 x i64> %x, <2 x i64> %y) {
+; SHA3-LABEL: xar_54:
+; SHA3:       // %bb.0:
+; SHA3-NEXT:    mov w8, #54 // =0x36
+; SHA3-NEXT:    xar v0.2d, v0.2d, v1.2d, w8
+; SHA3-NEXT:    ret
+;
+; NOSHA3-LABEL: xar_54:
+; NOSHA3:       // %bb.0:
+; NOSHA3-NEXT:    eor v0.16b, v0.16b, v1.16b
+; NOSHA3-NEXT:    ushr v1.2d, v0.2d, #54
+; NOSHA3-NEXT:    shl v0.2d, v0.2d, #10
+; NOSHA3-NEXT:    orr v0.16b, v0.16b, v1.16b
+; NOSHA3-NEXT:    ret
+    %a = xor <2 x i64> %x, %y
+    %b = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> <i64 10, i64 10>)
+    ret <2 x i64> %b
+}
+
+declare <2 x i64> @llvm.fshl.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
Index: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -423,6 +423,8 @@
   bool trySelectCastFixedLengthToScalableVector(SDNode *N);
   bool trySelectCastScalableToFixedLengthVector(SDNode *N);
 
+  bool SelectXAR(SDNode *N);
+
 // Include the pieces autogenerated from the target description.
 #include "AArch64GenDAGISel.inc"
 
@@ -4144,6 +4146,35 @@
   return true;
 }
 
+bool AArch64DAGToDAGISel::SelectXAR(SDNode *N) {
+  assert(N->getOpcode() == ISD::OR && "Expected OR instruction");
+
+  SDNode *N0 = cast<SDNode>(N->getOperand(0));
+  SDNode *N1 = cast<SDNode>(N->getOperand(1));
+
+  if (!(N0->getOpcode() == AArch64ISD::VSHL) || !(N1->getOpcode() == AArch64ISD::VLSHR))
+    return false;
+
+  if (!(N0->getOperand(0)->getOpcode() == ISD::XOR) || !(N1->getOperand(0)->getOpcode() == ISD::XOR))
+    return false;
+
+  SDNode *XOR = cast<SDNode>(N0->getOperand(0));
+  SDValue R1 = XOR->getOperand(0);
+  SDValue R2 = XOR->getOperand(1);
+  SDValue imm = N1->getOperand(1);
+
+  unsigned HsAmt = cast<ConstantSDNode>(N0->getOperand(1))->getZExtValue();
+  unsigned ShAmt = cast<ConstantSDNode>(N1->getOperand(1))->getZExtValue();
+
+  if (!(ShAmt + HsAmt == 64))
+    return false;
+
+  SDValue Ops[] = { R1, R2, imm };
+  CurDAG->SelectNodeTo(N, AArch64::XAR, MVT::i64, Ops);
+
+  return true;
+}
+
 void AArch64DAGToDAGISel::Select(SDNode *Node) {
   // If we have a custom node, we already have selected!
   if (Node->isMachineOpcode()) {
@@ -4212,6 +4243,10 @@
   case ISD::OR:
     if (tryBitfieldInsertOp(Node))
       return;
+    if (Subtarget->hasSHA3())
+      // Try matching XAR instruction here
+      if (SelectXAR(Node))
+        return;
     break;
 
   case ISD::EXTRACT_SUBVECTOR: {


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