[llvm] 0dc6468 - [InstCombine] Add bswap(logic_op(bswap(x), y)) regression test case; NFC
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun May 7 06:28:43 PDT 2023
Author: Austin Chang
Date: 2023-05-07T14:28:06+01:00
New Revision: 0dc6468edbcf5490ef606f7583f5a35e800d285d
URL: https://github.com/llvm/llvm-project/commit/0dc6468edbcf5490ef606f7583f5a35e800d285d
DIFF: https://github.com/llvm/llvm-project/commit/0dc6468edbcf5490ef606f7583f5a35e800d285d.diff
LOG: [InstCombine] Add bswap(logic_op(bswap(x), y)) regression test case; NFC
Fold the following case on IR InstCombine pass. This patch includes the new test cases for this optimization
bswap(logic_op(x, bswap(y))) -> logic_op(bswap(x), y)
bswap(logic_op(bswap(x), y)) -> logic_op(x, bswap(y))
bswap(logic_op(bswap(x), bswap(y))) -> logic_op(x, y) with multi-use
Differential Revision: https://reviews.llvm.org/D149577
Added:
Modified:
llvm/test/Transforms/InstCombine/bswap-fold.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/bswap-fold.ll b/llvm/test/Transforms/InstCombine/bswap-fold.ll
index 8183a0d709f33..5f6280bd24ced 100644
--- a/llvm/test/Transforms/InstCombine/bswap-fold.ll
+++ b/llvm/test/Transforms/InstCombine/bswap-fold.ll
@@ -539,6 +539,265 @@ define i64 @bs_and64i_multiuse(i64 %a, i64 %b) #0 {
}
+; Issue#62236
+; Fold: BSWAP( OP( BSWAP(x), y ) ) -> OP( x, BSWAP(y) )
+define i16 @bs_and_lhs_bs16(i16 %a, i16 %b) #0 {
+; CHECK-LABEL: @bs_and_lhs_bs16(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i16 @llvm.bswap.i16(i16 [[A:%.*]])
+; CHECK-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], [[B:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = tail call i16 @llvm.bswap.i16(i16 [[TMP2]])
+; CHECK-NEXT: ret i16 [[TMP3]]
+;
+ %1 = tail call i16 @llvm.bswap.i16(i16 %a)
+ %2 = and i16 %1, %b
+ %3 = tail call i16 @llvm.bswap.i16(i16 %2)
+ ret i16 %3
+}
+
+define i16 @bs_or_lhs_bs16(i16 %a, i16 %b) #0 {
+; CHECK-LABEL: @bs_or_lhs_bs16(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i16 @llvm.bswap.i16(i16 [[A:%.*]])
+; CHECK-NEXT: [[TMP2:%.*]] = or i16 [[TMP1]], [[B:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = tail call i16 @llvm.bswap.i16(i16 [[TMP2]])
+; CHECK-NEXT: ret i16 [[TMP3]]
+;
+ %1 = tail call i16 @llvm.bswap.i16(i16 %a)
+ %2 = or i16 %1, %b
+ %3 = tail call i16 @llvm.bswap.i16(i16 %2)
+ ret i16 %3
+}
+
+define i16 @bs_xor_lhs_bs16(i16 %a, i16 %b) #0 {
+; CHECK-LABEL: @bs_xor_lhs_bs16(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i16 @llvm.bswap.i16(i16 [[A:%.*]])
+; CHECK-NEXT: [[TMP2:%.*]] = xor i16 [[TMP1]], [[B:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = tail call i16 @llvm.bswap.i16(i16 [[TMP2]])
+; CHECK-NEXT: ret i16 [[TMP3]]
+;
+ %1 = tail call i16 @llvm.bswap.i16(i16 %a)
+ %2 = xor i16 %1, %b
+ %3 = tail call i16 @llvm.bswap.i16(i16 %2)
+ ret i16 %3
+}
+
+define i16 @bs_and_rhs_bs16(i16 %a, i16 %b) #0 {
+; CHECK-LABEL: @bs_and_rhs_bs16(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i16 @llvm.bswap.i16(i16 [[B:%.*]])
+; CHECK-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], [[A:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = tail call i16 @llvm.bswap.i16(i16 [[TMP2]])
+; CHECK-NEXT: ret i16 [[TMP3]]
+;
+ %1 = tail call i16 @llvm.bswap.i16(i16 %b)
+ %2 = and i16 %a, %1
+ %3 = tail call i16 @llvm.bswap.i16(i16 %2)
+ ret i16 %3
+}
+
+define i16 @bs_or_rhs_bs16(i16 %a, i16 %b) #0 {
+; CHECK-LABEL: @bs_or_rhs_bs16(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i16 @llvm.bswap.i16(i16 [[B:%.*]])
+; CHECK-NEXT: [[TMP2:%.*]] = or i16 [[TMP1]], [[A:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = tail call i16 @llvm.bswap.i16(i16 [[TMP2]])
+; CHECK-NEXT: ret i16 [[TMP3]]
+;
+ %1 = tail call i16 @llvm.bswap.i16(i16 %b)
+ %2 = or i16 %a, %1
+ %3 = tail call i16 @llvm.bswap.i16(i16 %2)
+ ret i16 %3
+}
+
+define i16 @bs_xor_rhs_bs16(i16 %a, i16 %b) #0 {
+; CHECK-LABEL: @bs_xor_rhs_bs16(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i16 @llvm.bswap.i16(i16 [[B:%.*]])
+; CHECK-NEXT: [[TMP2:%.*]] = xor i16 [[TMP1]], [[A:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = tail call i16 @llvm.bswap.i16(i16 [[TMP2]])
+; CHECK-NEXT: ret i16 [[TMP3]]
+;
+ %1 = tail call i16 @llvm.bswap.i16(i16 %b)
+ %2 = xor i16 %a, %1
+ %3 = tail call i16 @llvm.bswap.i16(i16 %2)
+ ret i16 %3
+}
+
+define i32 @bs_and_rhs_bs32(i32 %a, i32 %b) #0 {
+; CHECK-LABEL: @bs_and_rhs_bs32(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.bswap.i32(i32 [[B:%.*]])
+; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[A:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = tail call i32 @llvm.bswap.i32(i32 [[TMP2]])
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = tail call i32 @llvm.bswap.i32(i32 %b)
+ %2 = and i32 %a, %1
+ %3 = tail call i32 @llvm.bswap.i32(i32 %2)
+ ret i32 %3
+}
+
+define i32 @bs_or_rhs_bs32(i32 %a, i32 %b) #0 {
+; CHECK-LABEL: @bs_or_rhs_bs32(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.bswap.i32(i32 [[B:%.*]])
+; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[A:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = tail call i32 @llvm.bswap.i32(i32 [[TMP2]])
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = tail call i32 @llvm.bswap.i32(i32 %b)
+ %2 = or i32 %a, %1
+ %3 = tail call i32 @llvm.bswap.i32(i32 %2)
+ ret i32 %3
+}
+
+define i32 @bs_xor_rhs_bs32(i32 %a, i32 %b) #0 {
+; CHECK-LABEL: @bs_xor_rhs_bs32(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.bswap.i32(i32 [[B:%.*]])
+; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], [[A:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = tail call i32 @llvm.bswap.i32(i32 [[TMP2]])
+; CHECK-NEXT: ret i32 [[TMP3]]
+;
+ %1 = tail call i32 @llvm.bswap.i32(i32 %b)
+ %2 = xor i32 %a, %1
+ %3 = tail call i32 @llvm.bswap.i32(i32 %2)
+ ret i32 %3
+}
+
+define i64 @bs_and_rhs_bs64(i64 %a, i64 %b) #0 {
+; CHECK-LABEL: @bs_and_rhs_bs64(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.bswap.i64(i64 [[B:%.*]])
+; CHECK-NEXT: [[TMP2:%.*]] = and i64 [[TMP1]], [[A:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = tail call i64 @llvm.bswap.i64(i64 [[TMP2]])
+; CHECK-NEXT: ret i64 [[TMP3]]
+;
+ %1 = tail call i64 @llvm.bswap.i64(i64 %b)
+ %2 = and i64 %a, %1
+ %3 = tail call i64 @llvm.bswap.i64(i64 %2)
+ ret i64 %3
+}
+
+define i64 @bs_or_rhs_bs64(i64 %a, i64 %b) #0 {
+; CHECK-LABEL: @bs_or_rhs_bs64(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.bswap.i64(i64 [[B:%.*]])
+; CHECK-NEXT: [[TMP2:%.*]] = or i64 [[TMP1]], [[A:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = tail call i64 @llvm.bswap.i64(i64 [[TMP2]])
+; CHECK-NEXT: ret i64 [[TMP3]]
+;
+ %1 = tail call i64 @llvm.bswap.i64(i64 %b)
+ %2 = or i64 %a, %1
+ %3 = tail call i64 @llvm.bswap.i64(i64 %2)
+ ret i64 %3
+}
+
+define i64 @bs_xor_rhs_bs64(i64 %a, i64 %b) #0 {
+; CHECK-LABEL: @bs_xor_rhs_bs64(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.bswap.i64(i64 [[B:%.*]])
+; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], [[A:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = tail call i64 @llvm.bswap.i64(i64 [[TMP2]])
+; CHECK-NEXT: ret i64 [[TMP3]]
+;
+ %1 = tail call i64 @llvm.bswap.i64(i64 %b)
+ %2 = xor i64 %a, %1
+ %3 = tail call i64 @llvm.bswap.i64(i64 %2)
+ ret i64 %3
+}
+
+define <2 x i32> @bs_and_rhs_i32vec(<2 x i32> %a, <2 x i32> %b) #0 {
+; CHECK-LABEL: @bs_and_rhs_i32vec(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i32> @llvm.bswap.v2i32(<2 x i32> [[B:%.*]])
+; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], [[A:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = tail call <2 x i32> @llvm.bswap.v2i32(<2 x i32> [[TMP2]])
+; CHECK-NEXT: ret <2 x i32> [[TMP3]]
+;
+ %1 = tail call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %b)
+ %2 = and <2 x i32> %a, %1
+ %3 = tail call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %2)
+ ret <2 x i32> %3
+}
+
+define <2 x i32> @bs_or_rhs_i32vec(<2 x i32> %a, <2 x i32> %b) #0 {
+; CHECK-LABEL: @bs_or_rhs_i32vec(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i32> @llvm.bswap.v2i32(<2 x i32> [[B:%.*]])
+; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i32> [[TMP1]], [[A:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = tail call <2 x i32> @llvm.bswap.v2i32(<2 x i32> [[TMP2]])
+; CHECK-NEXT: ret <2 x i32> [[TMP3]]
+;
+ %1 = tail call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %b)
+ %2 = or <2 x i32> %a, %1
+ %3 = tail call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %2)
+ ret <2 x i32> %3
+}
+
+define <2 x i32> @bs_xor_rhs_i32vec(<2 x i32> %a, <2 x i32> %b) #0 {
+; CHECK-LABEL: @bs_xor_rhs_i32vec(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i32> @llvm.bswap.v2i32(<2 x i32> [[B:%.*]])
+; CHECK-NEXT: [[TMP2:%.*]] = xor <2 x i32> [[TMP1]], [[A:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = tail call <2 x i32> @llvm.bswap.v2i32(<2 x i32> [[TMP2]])
+; CHECK-NEXT: ret <2 x i32> [[TMP3]]
+;
+ %1 = tail call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %b)
+ %2 = xor <2 x i32> %a, %1
+ %3 = tail call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %2)
+ ret <2 x i32> %3
+}
+
+define i64 @bs_and_rhs_bs64_multiuse1(i64 %a, i64 %b) #0 {
+; CHECK-LABEL: @bs_and_rhs_bs64_multiuse1(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.bswap.i64(i64 [[B:%.*]])
+; CHECK-NEXT: [[TMP2:%.*]] = and i64 [[TMP1]], [[A:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = tail call i64 @llvm.bswap.i64(i64 [[TMP2]])
+; CHECK-NEXT: [[TMP4:%.*]] = mul i64 [[TMP2]], [[TMP3]]
+; CHECK-NEXT: ret i64 [[TMP4]]
+;
+ %1 = tail call i64 @llvm.bswap.i64(i64 %b)
+ %2 = and i64 %a, %1
+ %3 = tail call i64 @llvm.bswap.i64(i64 %2)
+ %4 = mul i64 %2, %3 ;increase use of logical op
+ ret i64 %4
+}
+
+define i64 @bs_and_rhs_bs64_multiuse2(i64 %a, i64 %b) #0 {
+; CHECK-LABEL: @bs_and_rhs_bs64_multiuse2(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.bswap.i64(i64 [[B:%.*]])
+; CHECK-NEXT: [[TMP2:%.*]] = and i64 [[TMP1]], [[A:%.*]]
+; CHECK-NEXT: [[TMP3:%.*]] = tail call i64 @llvm.bswap.i64(i64 [[TMP2]])
+; CHECK-NEXT: [[TMP4:%.*]] = mul i64 [[TMP1]], [[TMP3]]
+; CHECK-NEXT: ret i64 [[TMP4]]
+;
+ %1 = tail call i64 @llvm.bswap.i64(i64 %b)
+ %2 = and i64 %a, %1
+ %3 = tail call i64 @llvm.bswap.i64(i64 %2)
+ %4 = mul i64 %1, %3 ;increase use of inner bswap
+ ret i64 %4
+}
+
+define i64 @bs_all_operand64(i64 %a, i64 %b) #0 {
+; CHECK-LABEL: @bs_all_operand64(
+; CHECK-NEXT: [[TMP1:%.*]] = and i64 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT: ret i64 [[TMP1]]
+;
+ %1 = tail call i64 @llvm.bswap.i64(i64 %a)
+ %2 = tail call i64 @llvm.bswap.i64(i64 %b)
+ %3 = and i64 %1, %2
+ %4 = tail call i64 @llvm.bswap.i64(i64 %3)
+ ret i64 %4
+}
+
+define i64 @bs_all_operand64_multiuse_both(i64 %a, i64 %b) #0 {
+; CHECK-LABEL: @bs_all_operand64_multiuse_both(
+; CHECK-NEXT: [[TMP1:%.*]] = tail call i64 @llvm.bswap.i64(i64 [[A:%.*]])
+; CHECK-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.bswap.i64(i64 [[B:%.*]])
+; CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP1]], [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = tail call i64 @llvm.bswap.i64(i64 [[TMP3]])
+; CHECK-NEXT: call void @use.i64(i64 [[TMP1]])
+; CHECK-NEXT: call void @use.i64(i64 [[TMP2]])
+; CHECK-NEXT: ret i64 [[TMP4]]
+;
+ %1 = tail call i64 @llvm.bswap.i64(i64 %a)
+ %2 = tail call i64 @llvm.bswap.i64(i64 %b)
+ %3 = and i64 %1, %2
+ %4 = tail call i64 @llvm.bswap.i64(i64 %3)
+
+ call void @use.i64(i64 %1)
+ call void @use.i64(i64 %2)
+ ret i64 %4
+}
+
define i64 @bs_active_high8(i64 %0) {
; CHECK-LABEL: @bs_active_high8(
; CHECK-NEXT: [[TMP2:%.*]] = and i64 [[TMP0:%.*]], 255
@@ -806,6 +1065,7 @@ define i64 @bs_active_byte_12l(i64 %0) {
}
+declare i64 @use.i64(i64)
declare i16 @llvm.bswap.i16(i16)
declare i32 @llvm.bswap.i32(i32)
declare i64 @llvm.bswap.i64(i64)
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