[PATCH] D149814: [RISCV] Optimize i32 range checks

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D149814#4320593 <https://reviews.llvm.org/D149814#4320593>, @craig.topper wrote:

> My suggested patch lifted from AArch64/X86 with i8/i16 removed.
>
>   diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
>   index c020b27edf3e..f8fe17a9cfe3 100644
>   --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
>   +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
>   @@ -550,6 +550,23 @@ public:
>        return ISD::SIGN_EXTEND;
>      }
>    
>   +  bool shouldTransformSignedTruncationCheck(EVT XVT,
>   +                                            unsigned KeptBits) const override {
>   +    // For vectors, we don't have a preference..
>   +    if (XVT.isVector())
>   +      return false;
>   +
>   +    auto VTIsOk = [](EVT VT) -> bool {
>   +      return VT == MVT::i32 || VT == MVT::i64;
>   +    };
>   +
>   +    // We are ok with KeptBitsVT being byte/word/dword, what sext.w supports.
>   +    // XVT will be larger than KeptBitsVT.
>   +    // FIXME: Support Zbb?
>   +    MVT KeptBitsVT = MVT::getIntegerVT(KeptBits);
>   +    return VTIsOk(XVT) && VTIsOk(KeptBitsVT);
>   +  }
>   +
>      TargetLowering::ShiftLegalizationStrategy
>      preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N,
>                                         unsigned ExpansionFactor) const override {

Posted as https://reviews.llvm.org/D149977


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