[llvm] 44e7b8a - [AArch64] Tests for implicit zero patterns. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Fri May 5 07:12:57 PDT 2023
Author: David Green
Date: 2023-05-05T15:12:50+01:00
New Revision: 44e7b8aaf1369fbfb964585afc34f0abe9b1ebaf
URL: https://github.com/llvm/llvm-project/commit/44e7b8aaf1369fbfb964585afc34f0abe9b1ebaf
DIFF: https://github.com/llvm/llvm-project/commit/44e7b8aaf1369fbfb964585afc34f0abe9b1ebaf.diff
LOG: [AArch64] Tests for implicit zero patterns. NFC
See D149616
Added:
Modified:
llvm/test/CodeGen/AArch64/implicitly-set-zero-high-64-bits.ll
llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/implicitly-set-zero-high-64-bits.ll b/llvm/test/CodeGen/AArch64/implicitly-set-zero-high-64-bits.ll
index e24b4d649ff5..cd2d2c8619a9 100644
--- a/llvm/test/CodeGen/AArch64/implicitly-set-zero-high-64-bits.ll
+++ b/llvm/test/CodeGen/AArch64/implicitly-set-zero-high-64-bits.ll
@@ -32,3 +32,117 @@ entry:
ret <8 x i8> %vtbl11.i
}
+define <8 x i8> @tbl1v8i8(ptr nocapture noundef readonly %in, <8 x i8> noundef %idx) {
+; CHECK-LABEL: tbl1v8i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ldr q1, [x0]
+; CHECK-NEXT: shrn v1.8b, v1.8h, #4
+; CHECK-NEXT: tbl v0.8b, { v1.16b }, v0.8b
+; CHECK-NEXT: ret
+entry:
+ %0 = load <8 x i16>, ptr %in, align 2
+ %1 = lshr <8 x i16> %0, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
+ %vshrn_n = trunc <8 x i16> %1 to <8 x i8>
+ %vtbl1.i = shufflevector <8 x i8> %vshrn_n, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %vtbl11.i = tail call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %vtbl1.i, <8 x i8> %idx)
+ ret <8 x i8> %vtbl11.i
+}
+
+define <8 x i16> @addpv4i16(<4 x i16> noundef %a, <4 x i16> noundef %b) {
+; CHECK-LABEL: addpv4i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.2d, #0000000000000000
+; CHECK-NEXT: addp v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: mov v0.d[1], v2.d[0]
+; CHECK-NEXT: ret
+entry:
+ %vpadd_v2.i = tail call <4 x i16> @llvm.aarch64.neon.addp.v4i16(<4 x i16> %a, <4 x i16> %b)
+ %shuffle.i = shufflevector <4 x i16> %vpadd_v2.i, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i16> %shuffle.i
+}
+
+define <8 x i16> @addv4i16(<4 x i16> noundef %a, <4 x i16> noundef %b) {
+; CHECK-LABEL: addv4i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.2d, #0000000000000000
+; CHECK-NEXT: add v0.4h, v1.4h, v0.4h
+; CHECK-NEXT: mov v0.d[1], v2.d[0]
+; CHECK-NEXT: ret
+entry:
+ %add.i = add <4 x i16> %b, %a
+ %shuffle.i = shufflevector <4 x i16> %add.i, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i16> %shuffle.i
+}
+
+define <16 x i8> @rshrn(<8 x i16> noundef %a, <4 x i16> noundef %b) {
+; CHECK-LABEL: rshrn:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: rshrn v0.8b, v0.8h, #3
+; CHECK-NEXT: ret
+entry:
+ %vrshrn_n1 = tail call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %a, i32 3)
+ %shuffle.i = shufflevector <8 x i8> %vrshrn_n1, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x i8> %shuffle.i
+}
+
+define <16 x i8> @tbl1(<16 x i8> %a, <8 x i8> %b) {
+; CHECK-LABEL: tbl1:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.2d, #0000000000000000
+; CHECK-NEXT: tbl v0.8b, { v0.16b }, v1.8b
+; CHECK-NEXT: mov v0.d[1], v2.d[0]
+; CHECK-NEXT: ret
+entry:
+ %vtbl11 = tail call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %a, <8 x i8> %b)
+ %shuffle.i = shufflevector <8 x i8> %vtbl11, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x i8> %shuffle.i
+}
+
+define <2 x double> @fadd(double noundef %x, double noundef %y) {
+; CHECK-LABEL: fadd:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.2d, #0000000000000000
+; CHECK-NEXT: fadd d0, d0, d1
+; CHECK-NEXT: mov v2.d[0], v0.d[0]
+; CHECK-NEXT: mov v0.16b, v2.16b
+; CHECK-NEXT: ret
+entry:
+ %add = fadd double %x, %y
+ %vecinit1 = insertelement <2 x double> poison, double %add, i64 0
+ %vecinit2 = insertelement <2 x double> %vecinit1, double 0.0, i64 1
+ ret <2 x double> %vecinit2
+}
+
+define <16 x i8> @bsl(<4 x i16> noundef %a, <4 x i16> noundef %c, <4 x i16> noundef %d, <4 x i16> noundef %b) {
+; CHECK-LABEL: bsl:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v3.2d, #0000000000000000
+; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b
+; CHECK-NEXT: mov v0.d[1], v3.d[0]
+; CHECK-NEXT: ret
+entry:
+ %vbsl3.i = and <4 x i16> %c, %a
+ %0 = xor <4 x i16> %a, <i16 -1, i16 -1, i16 -1, i16 -1>
+ %vbsl4.i = and <4 x i16> %0, %d
+ %vbsl5.i = or <4 x i16> %vbsl4.i, %vbsl3.i
+ %1 = bitcast <4 x i16> %vbsl5.i to <8 x i8>
+ %shuffle.i = shufflevector <8 x i8> %1, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x i8> %shuffle.i
+}
+
+define <16 x i8> @load(ptr %a, <8 x i8> %b) {
+; CHECK-LABEL: load:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.2d, #0000000000000000
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ret
+entry:
+ %vtbl11 = load <8 x i8>, ptr %a
+ %shuffle.i = shufflevector <8 x i8> %vtbl11, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ ret <16 x i8> %shuffle.i
+}
+
+
+declare <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16>, i32)
+declare <4 x i16> @llvm.aarch64.neon.addp.v4i16(<4 x i16>, <4 x i16>)
diff --git a/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir b/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
index b4171d863c36..baa67dbb090f 100644
--- a/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
+++ b/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
@@ -32,6 +32,11 @@
ret void
}
+ define void @fadd(double %v, double %p) {
+ entry:
+ ret void
+ }
+
attributes #0 = { nocallback nofree nosync nounwind willreturn memory(none) }
...
@@ -395,4 +400,54 @@ body: |
RET_ReallyLR
...
+---
+name: fadd
+alignment: 4
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: fpr64, preferred-register: '' }
+ - { id: 1, class: fpr64, preferred-register: '' }
+ - { id: 2, class: fpr64, preferred-register: '' }
+ - { id: 3, class: fpr128, preferred-register: '' }
+ - { id: 4, class: fpr64, preferred-register: '' }
+ - { id: 5, class: fpr128, preferred-register: '' }
+ - { id: 6, class: fpr128, preferred-register: '' }
+ - { id: 7, class: fpr128, preferred-register: '' }
+ - { id: 8, class: fpr128, preferred-register: '' }
+ - { id: 9, class: fpr128, preferred-register: '' }
+liveins:
+ - { reg: '$d0', virtual-reg: '%0' }
+ - { reg: '$d1', virtual-reg: '%1' }
+body: |
+ bb.0.entry:
+ liveins: $d0, $d1
+ ; CHECK-LABEL: name: fadd
+ ; CHECK: liveins: $d0, $d1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
+ ; CHECK-NEXT: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[COPY1]], [[COPY]], implicit $fpcr
+ ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], killed [[COPY2]], %subreg.dsub
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], killed [[FADDDrr]], %subreg.dsub
+ ; CHECK-NEXT: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG1]], 1, killed [[INSERT_SUBREG]], 0
+ ; CHECK-NEXT: $q0 = COPY [[INSvi64lane]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
+ %1:fpr64 = COPY $d1
+ %0:fpr64 = COPY $d0
+ %2:fpr64 = nofpexcept FADDDrr %0, %1, implicit $fpcr
+ %3:fpr128 = MOVIv2d_ns 0
+ %4:fpr64 = COPY %3.dsub
+ %6:fpr128 = IMPLICIT_DEF
+ %5:fpr128 = INSERT_SUBREG %6, killed %4, %subreg.dsub
+ %8:fpr128 = IMPLICIT_DEF
+ %7:fpr128 = INSERT_SUBREG %8, killed %2, %subreg.dsub
+ %9:fpr128 = INSvi64lane %7, 1, killed %5, 0
+ $q0 = COPY %9
+ RET_ReallyLR implicit $q0
+
+...
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